HDSL2 for General Distribution Installation and Maintenance Practice HDSL New Enhanced Feature Overview61223HDSL2L2-5B B-3The support mechanisms for this feature can logically be divided into the following sixsegments:These support mechanisms are described in the following subsections.Splice Detection AlgorithmThe splice detection algorithm is designed to detect bad splices in training mode and datamode. The training mode detection is important if the splice is bad enough to prevent synchro-nization. In data mode, the detector will run periodically after synchronization is achieved.The HDSL2/HDSL4 transceiver monitors the loop for impedance changes that are of amagnitude to cause the received signal of the transceiver to be degraded. When a significantimpedance change is detected by the transceiver, the approximate distance from that trans-ceiver to the anomaly is recorded on the Splice Histogram screen by incrementing the appro-priate counter. When enough counts are accumulated at a particular distance, this distancewill be reported on the Splice Results screen.Screen SupportThe craft terminal port allows access to the splice detection menus via the Troubleshootingselection on the main menu. The Chronic Circuit Guidance selection takes the customer tothe main splice detection screen which describes the symptoms of a circuit with bad splices.This menu provides three choices:1. View Splice Results - This option will displays a screen that provides the results of thesplice detection tests. These results are calculated for each receiver point on the circuit. Ifmultiple bad splices are detected for a receiver, the worst is reported.2. View Histogram Screen - Choosing this option will take the customer to the HistogramScreen which displays the raw counters for each element at all receiver points.3. Reset Splice Detector - Choosing this option will allow the customer to reset the splicedetector. This choice requires a confirmation. The reset of the detector is done locally andthe command is sent across the EOC so that all units will also reset their detectors.EOC SupportTo get full coverage of the loop, all elements in the circuit run a local detector and thentransmit the results (local histogram counts and corresponding distance buffers) of thatdetection across the EOC to the terminating units (CO and RT). The terminating units thenuse these counts to present a result to the customer.FDL SupportAll the information available on the troubleshooting screens is also available via the FDL,allowing the detection to be monitored via network management utilities.• Splice Detection Algorithm • FDL Support• Screen Support • EEPROM Support• EOC Support • Event Support