MC96FM204/FM214April 7, 2016 Ver. 1.8 13513.4 RESET Noise CancellerThe Figure 13.2 is the noise canceller diagram for noise cancellation of RESET. It has the noise cancellationvalue of about 2us (@VDD=5V) to the low input of system reset.Figure 13.2 Reset noise canceller timer diagram13.5 Power On RESETWhen rising device power, the POR (Power On Reset) has a function to reset the device. If POR is used, itexecutes the device RESET function instead of the RESET IC or the RESET circuits.Figure 13.3 Fast VDD Rising TimeFigure 13.4 Internal RESET Release Timing On Power-UpVDDnPOR(Internal Signal)Internal RESETBOscillationBIT StartsBIT OverflowsSlow VDD Rise Time, min. 0.05V/mSVPOR=1.4V (Typ)VDDnPOR(Internal Signal)Internal RESETBOscillationBIT StartsBIT OverflowsFast VDD Rise Time, max. 30.0V/mst > TRNC t > TRNC t > TRNCt < TRNC t < TRNCAA’
