Abov MC96FM204 User Manual

Contents

Abov MC96FM204 User Manual Manual pdf 6 page image

MC96FM204/FM2146 April 7, 2016 Ver. 1.8Figure 11.6 8-Bit Timer/Counter 0 Example............................................................................................ 88Figure 11.7 8-Bit Timer 0 Block Diagram ................................................................................................ 89Figure 11.8 16-Bit Timer/Counter Mode for Timer 1 ............................................................................... 93Figure 11.9 16-Bit Timer/Counter 1 Example.......................................................................................... 93Figure 11.10 16-Bit Capture Mode for Timer 1 ....................................................................................... 94Figure 11.11 Input Capture Mode Operation for Timer 1 ........................................................................ 95Figure 11.12 Express Timer Overflow in Capture Mode ......................................................................... 95Figure 11.13 16-Bit PPG Mode for Timer 1............................................................................................. 96Figure 11.14 16-Bit PPG Mode Timming chart for Timer 1 ..................................................................... 97Figure 11.15 16-Bit Timer 1 Block Diagram ............................................................................................ 98Figure 11.16 16-Bit Timer/Counter Mode for Timer 2 ........................................................................... 103Figure 11.17 16-Bit Timer/Counter 2 Example ...................................................................................... 103Figure 11.18 16-Bit Capture Mode for Timer 2 ..................................................................................... 104Figure 11.19 Input Capture Mode Operation for Timer 2 ...................................................................... 105Figure 11.20 Express Timer Overflow in Capture Mode ....................................................................... 105Figure 11.21 16-Bit PPG Mode for Timer 2........................................................................................... 106Figure 11.22 16-Bit PPG Mode Timming chart for Timer 2 ................................................................... 107Figure 11.23 16-Bit Timer 2 Block Diagram .......................................................................................... 108Figure 11.24 Buzzer Driver Block Diagram ........................................................................................... 112Figure 11.25 SIO Block Diagram .......................................................................................................... 114Figure 11.26 SPI Transmit/Receive Timing Diagram at CPHA = 0 ....................................................... 116Figure 11.27 SPI Transmit/Receive Timing Diagram at CPHA = 1 ....................................................... 116Figure 11.28 8-bit ADC Block Diagram ................................................................................................. 121Figure 11.29 8-bit A/D Converter Timing Chart ..................................................................................... 121Figure 11.30 A/D Converter Operation Flow ......................................................................................... 122Figure 11.31 Analog Comparator Block Diagram ................................................................................. 125Figure 11.32 Operational Amplifier ....................................................................................................... 127Figure 12.1 IDLE Mode Release Timing by External Interrupt .............................................................. 130Figure 12.2 STOP Mode Release Timing by External Interrupt ............................................................ 131Figure 12.3 STOP Mode Release Flow ................................................................................................ 132Figure 13.1 RESET Block Diagram ...................................................................................................... 134Figure 13.2 Reset noise canceller timer diagram .................................................................................. 135Figure 13.3 Fast VDD Rising Time ....................................................................................................... 135Figure 13.4 Internal RESET Release Timing On Power-Up ................................................................. 135Figure 13.5 Configuration Timing when Power-on ................................................................................ 136Figure 13.6 Boot Process Wave Form .................................................................................................. 136Figure 13.7 Timing Diagram after RESET ............................................................................................ 138Figure 13.8 Oscillator generating waveform example ........................................................................... 138Figure 13.9 Block Diagram of BOD ....................................................................................................... 139Figure 13.10 Internal Reset at the power fail situation .......................................................................... 139Figure 13.11 Configuration timing when BOD RESET .......................................................................... 140Figure 13.12 LVI Diagram ..................................................................................................................... 140Figure 14.1 Block Diagram of On-Chip Debug System ......................................................................... 145Figure 14.2 10-bit Transmission Packet................................................................................................ 146Figure 14.3 Data Transfer on the Twin Bus .......................................................................................... 146Figure 14.4 Bit Transfer on the Serial Bus ............................................................................................ 147Figure 14.5 Start and Stop Condition .................................................................................................... 147Figure 14.6 Acknowledge on the Serial Bus ......................................................................................... 148