MC96FM204/FM214April 7, 2016 Ver. 1.8 137Table 13-2 Boot Process DescriptionProcess Description Remarks① -No Operation② -1st POR level Detection -about 1.4V③- (INT-OSC 8MHz/8)x256x28h Delay section (=10ms)-VDD input voltage must rise over than flash operatingvoltage for Config read-Slew Rate >= 0.05V/ms④ - Config read point-over 1.75V-Config Value is determined byWriting Option⑤ - Rising section to Reset Release Level -16ms point after POR or Ext_resetrelease⑥- Reset Release section (BIT overflow)i) after16ms, after External Reset Release (External reset)ii) 16ms point after POR (POR only)- BIT is used for Peripheral stability⑦ -Normal operation
