Acer Aspire L100 Service Manual

Also see for Aspire L100: User guide User guide

Contents

58 Chapter 4Power-On Self-Test (POST)Each time you turn on the system, the Power-on Self Test (POST) is initiated. Several items are tested duringPOST, but is for the most part transparent to the user.The Power-On Self Test (POST) is a BIOS procedure that boots the system, initializes and diagnoses thesystem components, and controls the operation of the power-on password option. If POST discovers errors insystem operations at power-on, it displays error messages on screen, generates a check point code at port80h or even halts the system if the error is fatal.The main components on the main board that must be diagnosed and/or initialized by POST to ensure systemfunctionality are as follows:q Microprocessor with built-in numeric co-processor and cache memory subsystemq Direct Memory Access (DMA) controllerq Interrupt systemq Three programmable timersq ROM subsystemq RAM subsystemq CMOS RAM subsystem and real time clock/calendar with battery backupq Onboard parallel interface controllerq Embedded hard disk interface and one diskette drive interfaceq Keyboard and auxiliary device controllersq 1.44M floppy controllerq I/O portsq One parallel portq One PS/2-compatible mouse portq One PS/2-compatible keyboard portNOTE: When Post executes a task, it uses a series of preset numbers called check points to be latched atport 80h, indicating the stages it is currently running. This latch can be read and shown on a debug board.The following table describes the BIOS common tasks carried out by POST. Each task is denoted by anunique check point number. For other unique check point numbers that are not listed in the table, refer to thecorresponding product service guide.Post Checkpoints List: The list may vary accordingly depending on your BIOS.Checkpoint DescriptionCFh Test CMOS R/W functionalityC0h Early chipset initialization:-Disable shadow RAM-Disable L2 cache (socket 7 or below)-Program basic chipset registersC1h Detect memory-Auto-detection of DRAM size, type and ECC.-Auto-detection of L2 cache (socket 7 or below)C3h Expand compressed BIOS code to DRAMC5h Call chipset hook to copy BIOS back to E000 & F000 shadow RAM.01h Expand the Xgroup codes locating in physical address 1000:002h Reserved