FabiaTech FR9100 User Manual
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FabIATech Corporation69Serial PortsThe ACEs (Asynchronous Communication Elements ACE1 to ACE2) are used toconvert parallel data to a serial format on the transmit side and convert serial datato parallel on the receiver side. The serial format, in order of transmission andreception, is a start bit, followed by five to eight data bits, a parity bit (ifprogrammed) and one, one and half (five-bit format only) or two stop bits. TheACEs are capable of handling divisors of 1 to 65535, and produce a 16x clock fordriving the internal transmitter logic.Provisions are also included to use this 16x clock to drive the receiver logic, alsoincluded in the ACE a completed MODEM control capability, and a processorinterrupt system that may be software tailored to the computing time required tohandle the communications link.The following table is a summary of each ACE accessible registerDLAB Port Address RegisterReceiver buffer (read)0 Base + 0Transmitter holding register (write)0 Base + 1 Interrupt EnabledX Base + 2 Interrupt identification (read only)X Base + 3 Line controlX Base + 4 MODEM controlX Base + 5 Line statusX Base + 6 MODEM statusX Base + 7 Scratched register1 Base + 0 Divisor latch (least significant byte)1 Base + 1 Divisor latch (most significant byte) Receiver Buffer Register (RBR)Bit 0-7: Received data byte (Read Only) Transmitter Holding Register (THR)Bit 0-7: Transmitter holding data byte (Write Only) Interrupt Enabled Register (IER)Bit 0: Enabled Received Data Available Interrupt (ERBFI) |
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