Garmin APOLLO GX SERIES Service Manual

Contents

Garmin AT Rev --6-2 GX Service Manual © 2004 Garmin AT• Parallel I/O ports• Watchdog Timer Unit (WDT)• JTAG test-logic unitThe two serial I/O ports on the microprocessor connect directly to the GPS receiver (J1) and thecommunication Comm board (J4) and are used for direct control and exchange of data between theCPU and these devices.The configuration jumper (J2) currently has only one function. The built-in test mode can be accessedby shorting pins 7 and 8 together, then turning on the GX unit. The built-in test mode can also beaccessed by turning the unit on while depressing the two outermost smart keys, or by issuing acommand by PC through the serial port.Reset/Watchdog/Battery Backup CircuitThe Maxim Max690A microprocessor supervisory IC (U1) provides a reset output (pin 7) duringpower-up, power-down, or during failing power conditions. Additionally, a reset pulse is output (pin 7)if the watchdog timer input (pin 6) has not been toggled within the specified time period (1-2.25 sec.).The Max690A also provides Vcc to battery switchover (Vout pin 1) for SRAM backup power when theGX unit is turned off. Backup power is supplied by a 3 V lithium backup battery.MemoryFlash Code ROMThe NAV board is designed to accept 2 MBIT (128K x 16), 4 MBIT (256K x 16), or 8 MBIT (512K x16) flash memories in the standard 48 pin TSOP package. There are two sites on the board (U102 &U103) that can allow code flash memory in the range of 2 MBIT to 16 MBIT depending on the partspopulated.The board design allows the use of Intel or AMD flash memories. Software routines are required forprogramming the flash memories on the board, and both the Intel and AMD parts are supported. Theflash memories include device and manufacturer codes that can be read. Therefore, the software candetermine the device types and execute the appropriate programming algorithms.The flash memories are soldered directly to the board; they are not placed in sockets. The flash mustbe programmed in-circuit. The 386EX and the on-board hardware supports utilizing the JTAG port forinitial flash programming. The parts are programmed with +5 volts, so a +12 volt power supply is notrequired.SRAMThe NAV board design uses either one or two 1 MBIT (128K x 8) low-power SRAMs (U104 & U105).The SRAM uses battery backup to save the contents when the unit is turned off.When using a single SRAM, the device is connected for use in byte mode. The chip selectconfiguration must be set to byte access by software.When using both SRAM devices, they are connected to allow word access. The BLE and BHEconnections allow for aligned and non-aligned word access as well as byte access.