IBM 71413SU - System x3950 M2 Reference

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18 IBM System x3950 M2 and x3850 M2 Technical IntroductionTable 9 lists the processors used in the x3950 M2 Datacenter models announced in January2008.Table 9 Processor used in the x3950 M2 Datacenter models announced January 2008All processors used in an x3850 M2 or x3950 M2 must be of the same type, speed, and L2/L3cache size. When adding an x3950 M2, all nodes must have either two or fourmicroprocessors installed.Xeon E7210 and E7300 Tigerton processors have two levels of cache on the processor die: Each pair of cores in the processor has either 2 MB, 3 MB, or 4 MB of shared L2 cache,for a total of 4 MB, 6 MB, or 8 MB of L2 cache. The L2 cache implements the AdvancedTransfer Cache technology. The L1 execution trace cache in each core is used to store micro-operations, decodedexecutable machine instructions. It serves those to the processor at rated speed. Thisadditional level of cache saves decode time on cache hits.The Tigerton processors do not have L3 cache.Model Standard CPU (dual-core or quad-core) CPU powerconsumptionPart number forCPU option7141-3AY 2 x 2.40 GHz Xeon E7330 Quad core 80 W 44E42427141-4AY 2x 2.93 GHz Xeon X7350 Quad Core 130W 44E42437141-3BY 2 x 2.40 GHz Xeon E7330 Quad core 80 W 44E42427141-4BY 2 x 2.93 GHz Xeon X7350 Quad core 130 W 44E42437141-3DY 2 x 2.40 GHz Xeon E7330 Quad core 80 W 44E42427141-4DY 2 x 2.93 GHz Xeon X7350 Quad core 130 W 44E42437141-3EY 2 x 2.40 GHz Xeon E7330 Quad core 80 W 44E42427141-4EY 2 x 2.93 GHz Xeon X7350 Quad core 130 W 44E4243