IBM 71413SU - System x3950 M2 Reference

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IBM System x3950 M2 and x3850 M2 Technical Introduction 19Figure 10 compares the layout of the Tigerton dual-core and quad-core processors.Figure 10 Comparing the dual-core and quad-core TigertonKey features of the processors used in the x3850 M2 and x3950 M2 include: Models with dual-core or quad-core processorsThe Tigerton dual-core processors are a concept similar to a two-way SMP system exceptthat the two processors, or cores, are integrated into one silicon die. This brings thebenefits of two-way SMP with less power consumption and faster data throughputbetween the two cores. To keep power consumption down, the resulting core frequency islower, but the additional processing capacity means an overall gain in performance.The Tigerton quad-core processors add two more cores onto the same die.Hyper-Threading Technology is not supported.Each core has separate L1 instruction and data caches, as well as separate executionunits (integer, floating point, and so on), registers, issue ports, and pipelines for each core.A multi-core processor achieves more parallelism than Hyper-Threading Technology,because these resources are not shared between the two cores.With double and quadruple the number of cores for the same number of sockets, it is evenmore important that the memory subsystem is able to meet the demand for datathroughput. The 34.1 GBps peak throughput of the x3850 M2 and x3950 M2 eX4Architecture with four memory cards is well-suited to dual-core and quad-core processors. 1066 MHz front-side busThe Tigerton Xeon MP uses two 266 MHz clocks, out of phase with each other by 90°, andusing both edges of each clock to transmit data. This is shown in Figure 11.Figure 11 Quad-pumped front-side busL1 InstructCacheL1 DataCache L2CacheQuad-core Xeon E7300 series(Code name: Tigerton)L2CacheL1InstructCacheL1DataCacheProcessorCoreL2CacheDual-core Xeon E7210(Code name: Tigerton)L1InstructCacheL1DataCacheProcessorCoreL2CacheProcessorCoreL1 InstructCacheL1 DataCacheL1 InstructCacheL1 DataCacheL1 InstructCacheL1 DataCacheProcessorCoreProcessorCoreProcessorCore266 MHz clock A266 MHz clock B