IBM 71413SU - System x3950 M2 Reference

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IBM System x3950 M2 and x3850 M2 Technical Introduction 9Updating the system BIOS in every node in a scalable system can be performed from theprimary node. The server diagnostics, as well as the RSA II and BMC firmware, must beindividually updated on each node, but this can be performed remotely, as described:– The RSA II firmware can be updated using the RSA II Web interface or IBM Director.– The server diagnostics and BMC firmware can be updated with an RSA II remoteconsole session using the remote diskette function. Disk drives installed in any of the x3950 M2 are seen by the operating system as normaldisk drives. You can only have a maximum of two optional ServeRAID-MR10k adapters in themultinode configuration. The drives in the other nodes will need to remain connectedusing the built-in SAS controller. All PCI Express slots and onboard Gigabit Ethernet ports in the x3950 M2 are visible tothe operating system, as well.A fully configured, four-node, scalable system with quad-core processors would have64 cores, 1024 GB of memory (using 8 GB DIMMs), 28 PCI Express adapters, 2.3 TB of rawdisk space and eight Gigabit Ethernet connections.Scalable systems setupCertain tasks must be performed before a multinode configuration can be operatedsuccessfully: All system firmware, including the system BIOS, diagnostics, BMC firmware and RSA IIfirmware, must be at the same level across all systems. Memory settings for HPMA, HAM, FAMM in BIOS must be standardized across allsystems in the multinode configuration while the nodes are still logically separate (that is,pre-merge). Refer to Table 11 on page 28 for details about this topic. You will need separate KVM connections to each node. Alternatively, you can configurethem using an RSA II remote console session. Post-merge settings that can be applied to the primary node are:– Advanced Setup - PCI settings– Passwords– Boot orderScalability ports and cablesNodes in an x3950 M2 multi-node complex are connected together by a number of scalabilitycables. These cables are attached to three SMP Expansion Ports (commonly referred to asscalability ports) on the rear of each system, as shown in Figure 6 on page 11.The scalability ports interface directly to the eX4 Architecture chipset and allow high speedcommunication between processors located in different chassis. The ports act like hardwareextensions to the processor local buses. They direct read and write cycles to the appropriatememory or I/O resources, as well as maintain cache coherency between the processors.These scalability ports are connected together with scalability cables to enable configurationof multinode scalable systems up to 16-way.Note: The US law restricting the export of high capacity servers was relaxed in 2002.Therefore, this restriction no longer affects the x3850 M2 and x3950 M2.