40 IBM BladeCenter PS703 and PS704 Technical Overview and Introductionprocessor-based systems is one of system-wide balance in which the POWER7 processorplays an important role.IBM has used innovative methods to achieve required levels of throughput and bandwidth.Areas of innovation for the POWER7 processor and POWER7 processor-based systemsinclude (but are not limited to) the following elements: On-chip L3 cache implemented in embedded dynamic random access memory (eDRAM) Cache hierarchy and component innovation Advances in memory subsystem Advances in off-chip signallingThe superscalar POWER7 processor design also provides a variety of other capabilities,including: Binary compatibility with the prior generation of POWER processors Support for PowerVM virtualization capabilities, including PowerVM Live Partition Mobilityto and from POWER6 and POWER6+™ processor-based systemsFigure 2-3 shows the POWER7 processor die layout with the major areas identified: eightPOWER7 processor cores, L2 cache, L3 cache and chip power bus Interconnect,simultaneous multiprocessing (SMP) links, GX++ interface, and two memory controllers.Figure 2-3 POWER7 processor architecture2.2.1 POWER7 processor overviewThe POWER7 processor chip is fabricated with the IBM 45 nm Silicon-On-Insulator (SOI)technology using copper interconnects, and implements an on-chip L3 cache using eDRAM.The POWER7 processor chip is 567 mm2 and is built using 1.2 billion components(transistors). Eight processor cores are on the chip, each with 12 execution units, 256 KB ofL2 cache, and access to up to 32 MB of shared on-chip L3 cache.For memory access, the POWER7 processor includes two DDR3 (Double Data Rate 3)memory controllers, each with four memory channels. To scale effectively, the POWER7processor uses a combination of local and global SMP links with high coherency bandwidthand makes use of the IBM dual-scope broadcast coherence protocol.C1CoreL24MB L3Memory Controller 1L2C1Core4MB L3Memory Controller 0C1CoreL24MB L3C1CoreL24MB L3C1CoreL24MB L3L2C1Core4MB L3L2C1Core4MB L3L2C1Core4MB L3SMPGX++ BridgeMemory buffersMemory buffers
