IBM p5 550 Technical Overview And Introduction

Also see for p5 550: Technical overview and introduction

Contents

Chapter 2. Architecture and technical overview 19Enhanced SMT featuresTo improve SMT performance for various workload mixes and provide robust quality ofservice, POWER5 provides two features: Dynamic resource balancing– The objective of dynamic resource balancing is to ensure that the two threadsexecuting on the same processor flow smoothly through the system.– Depending on the situation, the POWER5 processor resource balancing logic hasdifferent thread throttling mechanisms. Adjustable thread priority– Adjustable thread priority lets software determine when one thread should have agreater (or lesser) share of execution resources.– POWER5 supports eight software-controlled priority levels for each thread.ST operationNot all applications benefit from SMT. Having threads executing on the same processor willnot increase the performance of applications with execution unit limited performance orapplications that consume all the chip’s memory bandwidth. For this reason, the POWER5supports the ST execution mode. In this mode, the POWER5 processor gives all the physicalresources to the active thread, allowing it to achieve higher performance than a POWER4processor-based system at equivalent frequencies. Highly optimized scientific codes are oneexample where ST operation is ideal.Dynamic power managementIn current Complimentary Metal Oxide Semiconductor (CMOS) technologies, chip power isone of the most important design parameters. With the introduction of SMT, more instructionsexecute per cycle per processor core, thus increasing the core’s and the chip’s total switchingpower. To reduce switching power, POWER5 chips use a fine-grained, dynamic clock gatingmechanism extensively. This mechanism gates off clocks to a local clock buffer if dynamicpower management logic knows the set of latches driven by the buffer will not be used in thenext cycle. This allows substantial power saving with no performance impact. In every cycle,the dynamic power management logic determines whether a local clock buffer that drives aset of latches can be clock gated in the next cycle.In addition to the switching power, leakage power has become a performance limiter. Toreduce leakage power, the POWER5 chip uses transistors with low threshold voltage only incritical paths. The POWER5 chip also has a low-power mode, enabled when the systemsoftware instructs the hardware to execute both threads at the lowest available priority. In lowpower mode, instructions dispatch once every 32 cycles at most, further reducing switchingpower. The POWER5 chip uses this mode only when there is no ready task to run on eitherthread.2.1.1 POWER chip evolutionThe p5-550 system complies with the RS/6000 platform architecture, which is an evolution ofthe PowerPC Common Hardware Reference Platform (CHRP) specifications. Figure 2-3shows the POWER evolution.