IBM p5 550 Technical Overview And Introduction

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20 p5-550 Technical Overview and IntroductionFigure 2-3 POWER chip evolution2.1.2 CMOS, copper, and SOI technologyThe POWER5 processor design is a result of a close collaboration between IBM Systems andTechnology Group and IBM Microelectronics Technologies that enables IBM Sserver p5systems to give customers improved performance, reduced power consumption, anddecreased IT footprint size through logical partitioning. The POWER5 processor chip takesadvantage of IBM leadership technology. It is made using IBM 0.13- μ m-lithography CMOStechnology. The POWER5 processor also uses copper and silicon-on-insulator (SOI)technology to allow a higher operating frequency for improved performance yet with reducedpower consumption and improved reliability compared to processors not using thistechnology.2.2 Processor cardsIn the p5-550 system, the POWER5 chip has been packaged with the L3 cache chip into acost-effective Dual Chip Module (DCM) package. The storage structure for the POWER5 chipis a distributed memory architecture, which provides high memory bandwidth. Eachprocessor can address all memory and sees a single shared memory resource. As such, asingle DCM and its associated L3 cache and memory are packaged on a single processorcard. Access to memory behind another processor is accomplished through the fabric buses.The p5-550 supports up to two processor cards (each card is a 2-way). Each processor card32bit64bit Note: Not allprocessor speedsavailable on allmodelsPOWER41.0 to 1.3GHzPOWER4+1.2 to 1.9 GHzRS64-IV600 / 750pSeries p620, p660,and p680604e332 /375p615, p630,p650, p655, p670and p690Power3-II333 / 375 /450Models 270, B80, andPOWER3 SP NodesRS64125S70RS64-II262.5S7ARS64-II340H70RS64-III450F80, H80, M80, S80Power3200+SP Nodes+ SOI =SOICopper =F50p630, p650, p655,p670, and p6901.2 to1.9 GHzCore1.2 to1.9 GHzCoreShared L2Shared L2Distributed Switch0.13 microns2002-3–Larger L2–More LPARs–High-speed SwitchPOWER4+Shared L2Distributed Switch0.18 microns2001POWER4™–Distributed Switch–Shared L2–LPAR–Autonomic computing–Chip multiprocessing1.0 to1.3 GHzCore1.0 to1.3 GHzCoreShared L2Shared L2Distributed Switch0.18 microns2001POWER4™–Distributed Switch–Shared L2–LPAR–Autonomic computing–Chip multiprocessing1.0 to1.3 GHzCore1.0 to1.3 GHzCoreShared L2Distributed Switch0.13 microns2004POWER5TM–Larger L2 and L3 caches–Micro-partitioning–Enhanced Distributed Switch–Enhanced core parallelism–Improved floating-point–performance–Faster memory environmentMem Ctl1.5 to1.9 GHzCore1.5 to1.9 GHzCoreShared L2Shared L2Distributed Switch0.13 microns2004POWER5TM–Larger L2 and L3 caches–Micro-partitioning–Enhanced Distributed Switch–Enhanced core parallelism–Improved floating-point–performance–Faster memory environmentMem Ctl1.5 to1.9 GHzCore1.5 to1.9 GHzCore