IBM p5 550 Technical Overview And Introduction

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Contents

36 p5-550 Technical Overview and Introduction2.11 Service processorThe service processor (SP) is an embedded controller based on a PowerPC 405GPprocessor (PPC405) implementation running the SP internal operating system. The SPoperating system contains specific programs and device drivers for the SP hardware(Figure 2-13 on page 36).The p5-550 uses the SP implementation. The key components include a FSP-Base (FSP-B)and an Extender chipset (FSP-E). FSP-B and FSP-E are implemented on a dedicated card.Figure 2-13 Service processor logical diagram2.11.1 Service processor baseThe PPC405 core is 5-stage pipeline instruction processor and contains 32-bit generalpurpose registers. The Flash ROM contains a compressed image of a software load.The SP base unit offers the following connections: Two Ethernet Media Access Controller3 (MAC3) cores, which is a generic implementationof the Ethernet Media Access (MAC) protocol compliant with ANSI/IEEE 802.3, IEEE802.3u, ISO/IEC 8802.3 CSMA/CD standard. The Ethernet MAC3 supports both halfduplex (CSMA/CD) and full duplex operation at 10/100 Mbps. Both Ethernet port arevisible only to the service processor. Two serial interfaces, accessible only though the serial ports of p5-550 on the rear side. Atthe time of writing, the System Management Interface (SMI) is usable if a connection isestablished to serial port 1. Terminals connected to serial port 2 receive only bootsequence information without manual interaction. When the HMC is connected to the SP,the serial ports are disabled and do not provide any external connection.HMC1HMC2RJ45Ethn.1Ethn.2RJ45S1S2SPCN1SPCN2System planarRear portsFSPMUXRear serialports systemUART#2UART#1UART#3UART#4FSP-EFSP-BFlashNVRAMDDRInterface DDR64 MBALE SRAM1 MBFlash ROM48 MBNVRAMcontroller