318 Keysight M8000 Series of BER Test Solutions User Guide6 Setting up AnalyzerClock SetupTo measure the Bit Error Rate with the Analyzer, the bit rate of the datastream must be known. Depending on the options the instrument isdelivered with, you could use either an external clock source for theAnalyzer (for example, the clock from the generator), or extract the clocksignal from the incoming data (CDR mode).CDR mode does not work for all kinds of data patterns. For example, if thedevice under test sends only blocks of ones and zeros, there are notransitions in the data stream and the M8020A/M8030A cannot recoverthe clock.Also, if you are testing bursts, there are some special considerations forsetting up CDR.How does Clock Data Recovery Work?In CDR mode, the CDR has to recover the clock from the incoming data. Todo this, the hardware has to decide whether the voltage at the inputconnector is a logical '1' or '0' and then recover the clock from thedetected transitions.Clock Data Recovery (CDR) is a special kind of Phase Locked Loop (PLL),which recovers clock signal of a data stream. It is a regulatory loop, whichsynchronizes the local oscillator with an external reference, in this case theincoming data stream.Phase Locked LoopA PLL has three parts: a phase detector, a loop filter, and a VoltageControlled Oscillator (VCO). The phase detector has two inputs, and oneoutput, which is proportional to the phase difference of the inputs. Theloop filter is a low pass filter which attenuates the higher frequencies fromthe output of the phase detector. The VCO is an adjustable oscillator whichchanges the output frequency depending on its input voltage. The diagrambelow shows a simple PLL.
