Keysight EXG and MXG X-Series Signal Generators User’s Guide 295Digital Signal Interface Module (Option 003/004)Clock TimingFigure 10-6 Clock Timing for a Serial Port ConfigurationClock Timing for Phase and Skew AdjustmentsThe N5102A module provides phase and skew adjustments for the clock relative to the data andcan be used to align the clock with the valid portion of the data. The phase has a 90 degreeresolution (0, 90, 180, and 270 degree selections) for clock rates from 10 to 200 MHz and a 180degree resolution (0 and 180 degree selections) for clock rates below 10 MHz and greater than 200MHz.The skew is displayed in nanoseconds with a maximum range of ±5 ns using a maximum of ±127discrete steps. Both the skew range and the number of discrete steps are variable with adependency on the clock rate. The skew range decreases as the clock rate is increased andincreases as the clock rate is decreased. The maximum skew range is reached at a clock rate ofapproximately 99 MHz and is maintained down to a clock rate of 25 MHz. For clock rates below 25MHz, the skew adjustment is unavailable.A discrete step is calculated using the following formula:The number of discrete steps required to reach the maximum skew range decreases at lowerfrequencies. For example, at a clock rate of 50 MHz, 127 steps would exceed the maximum skewrange of ±5 ns, so the actual number of discrete steps would be less than 127.Figure 10-7 is an example of a phase and skew adjustment and shows the original clock and itsphase position relative to the data after each adjustment. Notice that the skew adjustment adds tothe phase setting.Clock4 bits per word1 SampleFrame MarkerData Bits1256 Clock Rate×------------------------------------------
