Lattice Semiconductor ECP5 User Manual

Also see for ECP5 Versa: User guide User guide Technical note Technical notes Usage Guide

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Lattice Semiconductor ECP5 User Manual Manual pdf 10 page image

ECP5 VIP Processor BoardEvaluation Board User Guide© 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.10 FPGA-EB-02001-1.2Upstream and Downstream interfaceFigure 4.3 shows the block diagram of the Upstream and Downstream connector. Upstream and Downstreamconnectors act as board to board connector and are used to interface the ECP5 VIP processor board to any otherexternal boards for bridging applications. These connectors support interfaces, such as LVDS, MIPI, SPI, JTAG, SERDESand general purpose interface.LFE5UM-85F-BG756(U17)Downstreamconnector 1 ( J12)Downstreamconnector 2 (J13)LVDS/MIPI Rx,SPI, JTAG,SERDES RxMIPI/LVDS Tx,GPIO I/FLVDS/MIPI Tx,SPI, JTAG,SERDES TxUpstreamconnector 2 (J11)Upstreamconnector 1 (J10)LVDS/MIPI Rx,GPIO I/FFigure 4.3. Upstream and Downstream ConnectorispClock5406D InterfaceFigure 4.4 shows the block diagram of the ispClock5406D interface. For more information on Lattice ispClock, visitwww.latticesemi.com/ispclock.The ispClock5406D device can be programmed using JTAG through FTDI interface. This circuitry is used as a referenceclock generation circuit for the ECP5 SERDES interface. The input clock source for the reference clock generation circuitcan be onboard oscillator or the PLL output from ECP5 FPGA which can be selected by the ref_sel input of theispClock5406D.ispClock5406D(U53)LFE5UM-85F-BG756(U17)156.25 MHz Clock OSC(X4)JTAGRef_SelECP5_PLLSERDES RefCLK LFE5UM-85F-BG756(U17)Figure 4.4. ispClock5406D Interface