Lattice Semiconductor ECP5 User Manual

Also see for ECP5 Versa: User guide User guide Technical note Technical notes Usage Guide

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Lattice Semiconductor ECP5 User Manual Manual pdf 14 page image

ECP5 VIP Processor BoardEvaluation Board User Guide© 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.14 FPGA-EB-02001-1.26. ECP5 I/O Ball Mapping to ConnectorsTable 6.1. Upstream Connector MappingJ10 J11Pin number onConnector Net Name ECP5 Ball Pin Number onConnector Net Name ECP5 Ball1 3V3 — 1 3V3 —2 5V — 2 3V3 —3 3V3 — 3 3V3 —4 5V — 4 3V3 —5 GND — 5 UP_GPIO9 F296 5V — 6 UP_GPIO17 A137 LVDS_CP P27 7 UP_GPIO10 F288 GND — 8 UP_GPIO18 A89 LVDS_CN P26 9 UP_GPIO1 C2910 LVDS_D2P J30 10 UP_GPIO19 F911 GND — 11 UP_GPIO2 C3012 LVDS_D2N K30 12 UP_GPIO20 D913 LVDS_D0P D30 13 LDI_RX_D3_P F3214 GND — 14 UP_GPIO21 C915 LVDS_D0N D31 15 LDI_RX_D3_N H3216 LVDS_D3P L31 16 UP_GPIO22 A917 GND — 17 GND —18 LVDS_D3N L30 18 GND —19 LVDS_D1P K32 19 GND —20 GND — 20 GND —21 LVDS_D1N L32 21 LDI_RX_D2_P J2922 2V5 — 22 GND —23 GND — 23 LDI_RX_D2_N K2924 2V5 — 24 UP_GPIO25 C1025 DIR_GPIO3 — 25 UP_GPIO33 D1326 GND — 26 UP_GPIO26 B1027 UP_MCLK — 27 UP_GPIO34 C1328 GSRN AH1 28 UP_GPIO27 A1029 UP_SISPI — 29 LDI_RX_D0_P K2730 UP_GPIO48 C16 30 UP_GPIO28 E1131 UP_SPISO — 31 LDI_RX_D0_N K2632 UP_GPIO49 B16 32 UP_GPIO29 D1133 UP_CSSPIN — 33 GND —34 GND — 34 UP_GPIO30 C1135 UP_CDONE — 35 GND —36 HDRXP0_D1CH0 AM17 36 GND —37 UP_CRESETB — 37 LDI_RX_D1_P J2638 HDRXN0_D1CH0 AM18 38 GND —39 DIR_GPIO4 — 39 LDI_RX_D1_N J2740 GND — 40 GND —41 SCL AG1 41 UP_GPIO31 B1142 HDRXP0_D1CH1 AM20 42 UP_GPIO39 B14