Lattice Semiconductor MachXO2 User Manual
Also see for MachXO2 Series: User guideUsage GuideProgramming and Configuration Usage GuideUser guideQuick start
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Functional DescriptionIPUG92_01.2, October 2012 11 LPDDR SDRAM Controller User’s GuideFigure 2-5. User-Side Read OperationREADAREADA is treated in the same way as a READ command except that the core issues a Read with Auto Prechargecommand to the memory instead of a READ command. This makes the memory automatically close the currentrow after completing the read operation.AUTO REFRESHSince LPDDR memories have at least an 8-deep Auto Refresh command queue as per the JEDEC specification,the Lattices LPDDR memory controller core can support up to eight Auto Refresh commands in one burst. Thecore has an internal Auto Refresh Generator that sends out a set of consecutive Auto Refresh commands to thememory at once when it reaches the time period of the refresh intervals (tREFI ) times the Auto Refresh burst countselected in the IPexpress GUI. It is recommended that the maximum number be used if the LPDDR interfacethroughput is a major concern of the system. If it is set to eight, for example, the core will send a set of eight con-secutive Auto Refresh commands to the memory once it reaches the time period of the eight refresh intervals (tREFIx 8). Bursting refresh cycles increases the LPDDR bus throughput because it helps keep core intervention to aminimum. Upon completion of an Auto Refresh burst, the controller will automatically retrain the I/Os if the periodicretraining of the I/Os is selected from the IPexpress GUI.SELF REFRESHThe self refresh command comes as a set of two in compliance to JEDEC protocol: self refresh entry and selfrefresh exit. The user should always use them as a set, a self refresh exit should always follow a self refresh entry.To minimize power, the user has the option to turn the memory clock off during self refresh operations. This is auser-programmable parameter, and when set, the controller will automatically turn off the memory clock. To mini-mize the power even further, the controller will refresh half or a quarter of the memory if it is set through an MRScommand.Power Down and Deep Power DownThe power down commands come as a set of two in compliance to JEDEC protocol: entry and exit. The usershould always use them as a set an exit should always follow an entry. To minimize power, the user has the optionto turn the memory clock off during power-down operations. For deep power entry, the controller will re-initialize thememory upon exiting the deep power down state, and retrain the I/Os if it is selected from the GUI.User Commands for Wishbone InterfaceThe LPDDR controller has a GUI selectable interface compliant to two port WISHBONE bus. Port_0 is used forread/writes and port_1 for programming the memory.read_data_validread_data D0 D1read_data_validD0 D1 D1 D1read_dataBurst length = 4D0Burst length = 2Burst length = 8 |
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