Lattice Semiconductor MachXO2 User Manual
Also see for MachXO2 Series: User guideUsage GuideProgramming and Configuration Usage GuideUser guideQuick start
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IPUG92_01.2, October 2012 20 LPDDR SDRAM Controller User’s GuideThis chapter provides information on how to generate the LPDDR SDRAM IP core using the Diamond IPexpresstool, and how to include the core in a top-level design.The LPDDR SDRAM IP core can be used in the MachXO2 device family. For example information and knownissues on this IP core see the Lattice LPDDR IP ReadMe document. This file is available once the core is installedin Diamond. The document provides information on creating an evaluation version of the core for use in simulation.Users may download and generate the LPDDR SDRAM IP core and fully evaluate the core through functional sim-ulation and implementation (synthesis, map, place and route) without an IP license. The LPDDR SDRAM IP corealso supports Lattice’s IP hardware evaluation capability, which makes it possible to create versions of the IP corethat operate in hardware for a limited time (approximately four hours) without requiring an IP license. See “Hard-ware Evaluation” on page 26 for further details. However, a license is required to enable timing simulation, to openthe design in the Diamond EPIC tool, and to generate bitstreams that do not include the hardware evaluation time-out limitation.Getting StartedThe LPDDR SDRAM IP core is available for download from the Lattice’s IP Server using the IPexpress tool. The IPfiles are automatically installed using ispUPDATE technology in any customer-specified directory. After the IP corehas been installed, the IP core will be available in the IPexpress GUI dialog box shown in Figure 4-1.The IPexpress tool GUI dialog box for the LPDDR SDRAM IP core is shown in Figure 4-1. To generate a specific IPcore configuration the user specifies:• Project Path – Path to the directory where the generated IP files will be loaded.• File Name – “username” designation given to the generated IP core and corresponding folders and files.• Module Output – Verilog or VHDL.• Device Family – Device family to which IP is to be targeted. Only families that support the particular IP core arelisted.• Part Name – Specific targeted part within the selected device family.Chapter 4:IP Core Generation |
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