Lattice Semiconductor MachXO2 User Manual
Also see for MachXO2 Series: User guideUsage GuideProgramming and Configuration Usage GuideUser guideQuick start
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Contents
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IPUG92_01.2, October 2012 28 LPDDR SDRAM Controller User’s GuideThis chapter provides application support information for the MachXO2 LPDDR SDRAM Controller IP core.Core ImplementationThis section describes the major factors that are important for a successful LPDDR memory controller implementa-tion.Understanding PreferencesThe following preferences are found in the provided logical preference files (.lpf):• FREQUENCY – The LPDDR SDRAM Controller IP core is normally over-constrained for obtaining optimal f MAXresults. The post-route trace preference file contains the preferences that have the real performance targets, andit should be used to validate the timing results.• IOBUF – The IOBUF preference assigns the required I/O types to the LPDDR I/O pads.• LOCATE – For all MachXO2 devices the memory data and data strobe pins are located at the right side of thedevice. For this reason these I/Os are grouped and locked to Bank 1.Chapter 5:Application Support |
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