Lattice Semiconductor MachXO2 User Manual
Also see for MachXO2 Series: User guideUsage GuideProgramming and Configuration Usage GuideUser guideQuick start
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Contents
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IPUG92_01.2, October 2012 5 LPDDR SDRAM Controller User’s GuideOverviewThe LPDDR memory controller consists of two major parts: the controller core logic module and the I/O logic mod-ule. This section briefly describes the operation of each of these modules. Figure 2-1 provides a high-level blockdiagram illustrating the main functional blocks and the technology used to implement the LPDDR SDRAM Control-ler IP core functions.Figure 2-1. LPDDR SDRAM Controller Block DiagramThe core module has several functional sub-modules: Initialization Block, Command Decode Logic Block, Com-mand Application Logic Block, Data Control Block and I/O Training Block. LPDDR I/O modules provide the PHYinterface to the memory device. This block mostly consists of MachXO2 device I/O primitives supporting compli-ance to LPDDR electrical and timing requirements.Initialization BlockThe Initialization Block performs the LPDDR memory initialization sequence as defined by the JEDEC protocol.After power-on or a normal reset of the LPDDR controller, memory must be initialized before sending any com-mand to the Controller. It is the user’s responsibility to assert the init_start input to the LPDDR controller to start thememory initialization sequence. The completion of initialization is indicated by the init_done output provided by thisblock.Configuration InterfaceCommandDecodeLogicInitializationData ControlI/O Training I/Osclk_inrst_ncmdaddrcmd_validinit_startdataindmselar_burst_cntcmd_rdydata_rdyinit_doneread_dataread_data_validtRC tRP tRCD tSRRtXPem_ddr_cs_nem_ddr_ras_nem_ddr_we_nem_ddr_cas_nem_ddr_ckeem_ddr_clkem_ddr_addrem_ddr_baem_ddr_dmem_ddr_dataem_ddr_dqsCommandApplicationLogicChapter 2:Functional Description |
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