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NEC PD78052 User Manual

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Contents
  1. Table Of Contents
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. Table Of Contents
  8. Table Of Contents
  9. Table Of Contents
  10. Table Of Contents
  11. Table Of Contents
  12. Table Of Contents
  13. Table Of Contents
  14. Table Of Contents
  15. Table Of Contents
  16. Table Of Contents
  17. Table Of Contents
  18. Table Of Contents
  19. Table Of Contents
  20. CHAPTER 1 GENERAL ( PD78054 Subseries)
  21. Applications
  22. Quality Grade
  23. Pin Configuration (Top View)
  24. K/0 Series Expansion
  25. Block Diagram
  26. Outline of Function
  27. Differences between Standard Quality Grade Products and (A) Products
  28. CHAPTER 2 GENERAL ( PD78054Y Subseries)
  29. Ordering Information
  34. Mask Options
  35. CHAPTER 3 PIN FUNCTION ( PD78054 Subseries)
  36. PROM programming mode pins (PROM versions only)
  37. Description of Pin Functions
  38. P10 to P17 (Port 1)
  39. P30 to P37 (Port 3)
  40. P40 to P47 (Port 4)
  41. P70 to P72 (Port 7)
  42. P120 to P127 (Port 12)
  43. AV DD
  44. Input/output Circuits and Recommended Connection of Unused Pins
  45. Pin Input/Output Circuit of List
  46. CHAPTER 4 PIN FUNCTION ( PD78054Y Subseries)
  48. P00 to P07 (Port 0)
  49. P20 to P27 (Port 2)
  51. P50 to P57 (Port 5)
  53. P130 and P131 (Port 13)
  54. X1 and X2
  55. Pin Input/Output Circuit Types
  57. CHAPTER 5 CPU ARCHITECTURE
  58. Memory Map ( PD78053, 78053Y)
  59. Memory Map ( PD78054, 78054Y)
  60. Memory Map ( PD78P054)
  61. Memory Map ( PD78055, 78055Y)
  62. Memory Map ( PD78056, 78056Y)
  63. Memory Map ( PD78058, 78058Y)
  64. Memory Map ( PD78P058, PD78P058Y)
  65. Internal program memory space
  66. Internal data memory space
  67. Data memory addressing
  68. Data Memory Addressing ( PD78053, 78053Y)
  69. Data Memory Addressing ( PD78054, 78054Y)
  70. Data Memory Addressing ( PD78P054)
  71. Data Memory Addressing ( PD78055, 78055Y)
  72. Data Memory Addressing ( PD78056, 78056Y)
  73. Data Memory Addressing ( PD78058, 78058Y)
  74. Data Memory Addressing ( PD78P058, 78P058Y)
  75. Processor Registers
  76. Internal High-Speed RAM Area
  77. Stack Pointer Configuration
  78. General registers
  79. General Register Configuration
  80. Special Function Register (SFR)
  81. Special-Function Register List
  82. Instruction Address Addressing
  83. Immediate addressing
  84. Table indirect addressing
  85. Operand Address Addressing
  86. Register addressing
  87. Direct addressing
  88. Short direct addressing
  89. Special-Function Register (SFR) addressing
  90. Register indirect addressing
  91. Based addressing
  92. Based indexed addressing
  93. CHAPTER 6 PORT FUNCTIONS
  94. Port Functions ( PD78054 subseries)
  95. Port Functions ( PD78054Y subseries)
  96. Port Configuration
  97. P00 and P07 Block Diagram
  98. Port 1
  99. Port 2 ( PD78054 Subseries)
  100. P22 and P27 Block Diagram
  101. Port 2 ( PD78054Y Subseries)
  103. Port 3
  104. Port 4
  105. Port 5
  106. Port 6
  107. P60 to P63 Block Diagram
  108. Port 7
  109. P71 and P72 Block Diagram
  110. Port 12
  111. Port 13
  112. Port Function Control Registers
  113. Port Mode Register and Output Latch Settings when Using Dual-Functions
  114. Port Mode Register Format
  115. Pull-Up Resistor Option Register Format
  116. Memory Expansion Mode Register Format
  117. Key Return Mode Register Format
  118. Port Function Operations
  119. Operations on input/output port
  120. CHAPTER 7 CLOCK GENERATOR
  121. Block Diagram of Clock Generator
  122. Clock Generator Control Register
  123. Processor Clock Control Register Format
  124. Relationship between CPU Clock and Minimum Instruction Execution Time
  125. Oscillation Mode Selection Register Format
  126. System Clock Oscillator
  127. Subsystem clock oscillator
  128. Scaler
  129. Clock Generator Operations
  130. Main system clock operations
  131. Subsystem clock operations
  132. System clock and CPU clock switching procedure
  133. CHAPTER 8 16-BIT TIMER/EVENT COUNTER
  134. Timer/Event Counter Operations
  135. Bit Timer/Event Counter Functions
  136. Bit Timer/Event Counter Square-Wave Output Ranges
  137. Bit Timer/Event Counter Configuration
  138. Bit Timer/Event Counter Output Control Circuit Block Diagram
  139. INTP0/TI00 Pin Valid Edge and CR00 Capture Trigger Valid Edge
  140. Bit Timer/Event Counter Control Registers
  141. Timer Clock Selection Register 0 Format
  142. Bit Timer Mode Control Register Format
  143. Capture/Compare Control Register 0 Format
  144. Bit Timer Output Control Register Format
  145. Port Mode Register 3 Format
  146. External Interrupt Mode Register 0 Format
  147. Sampling Clock Select Register Format
  148. Bit Timer/Event Counter Operations
  149. Interval Timer Configuration Diagram
  150. PWM output operations
  151. Control Register Settings for PWM Output Operation
  152. Example of D/A Converter Configuration with PWM Output
  153. PPG output operations
  154. Pulse width measurement operations
  155. Configuration Diagram for Pulse Width Measurement by Free-Running Counter
  156. Control Register Settings for Two Pulse Width Measurements with Free-Running Counter
  157. Two Capture Registers (with Rising Edge Specified)
  158. Control Register Settings for Pulse Width Measurement by Means of Restart
  159. External event counter operation
  160. External Event Counter Configuration Diagram
  161. Square-wave output operation
  162. Square-Wave Output Operation Timing
  163. One-shot pulse output operation
  164. Timing of One-Shot Pulse Output Operation Using Software Trigger
  165. Control Register Settings for One-Shot Pulse Output Operation Using External Trigger
  166. Bit Timer/Event Counter Operating Precautions
  167. Capture Register Data Retention Timing
  168. Operation Timing of OVF0 Flag
  169. CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2
  170. Bit Timer/Event Counters 1 and 2 Interval Times
  171. Bit Timer/Event Counters 1 and 2 Square-Wave Output Ranges
  172. bit timer/event counter mode
  173. Bit Timer/Event Counters 1 and 2 Configurations
  174. Bit Timer/Event Counters 1 and 2 Block Diagram
  175. Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 1
  176. Bit Timer/Event Counters 1 and 2 Control Registers
  177. Timer Clock Select Register 1 Format
  178. Bit Timer Mode Control Register 1 Format
  181. Bit Timer/Event Counters 1 and 2 Operations
  182. Bit Timer/Event Counter 1 Interval Time
  183. Bit Timer/Event Counter 2 Interval Time
  184. External Event Counter Operation Timings (with Rising Edge Specified)
  187. Interval Timer Operation Timing
  188. Interval Times when 2-Channel 8-Bit Timer/ Event Counters (TM1 and TM2) are Used as 16-Bit Timer/Event Counter
  190. Square-Wave Output Ranges when 2-Channel 8-Bit Timer/ Event Counters (TM1 and TM2 are Used as 16-Bit Timer/Event Counter
  191. Cautions on 8-Bit Timer/Event Counters 1 and 2
  192. Event Counter Operation Timing
  193. CHAPTER 10 WATCH TIMER
  194. Watch Timer Configuration
  195. Watch Timer Block Diagram
  196. Timer Clock Select Register 2 Format
  197. Watch Timer Mode Control Register Format
  198. Watch Timer Operations
  199. CHAPTER 11 WATCHDOG TIMER
  200. Interval Times
  201. Watchdog Timer Configuration
  202. Watchdog Timer Control Registers
  204. Watchdog Timer Mode Register Format
  205. Watchdog Timer Operations
  206. Interval timer operation
  207. CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT
  208. Clock Output Control Circuit Configuration
  209. Clock Output Function Control Registers
  210. Timer Clock Select Register 0 Format
  212. CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT
  213. Buzzer Output Function Control Registers
  216. CHAPTER 14 A/D CONVERTER
  217. A/D Converter Block Diagram
  218. A/D Converter Control Registers
  219. A/D Converter Mode Register Format
  220. A/D Converter Input Select Register Format
  221. External Interrupt Mode Register 1 Format
  222. A/D Converter Operations
  223. A/D Converter Basic Operation
  224. Input voltage and conversion results
  225. A/D converter operating mode
  226. A/D Conversion by Software Start
  227. A/D Converter Cautions
  228. Analog Input Pin Disposition
  229. A/D Conversion End Interrupt Request Generation Timing
  230. CHAPTER 15 D/A CONVERTER
  231. D/A Converter Configuration
  232. D/A Converter Control Registers
  233. Operations of D/A Converter
  234. Cautions Related to D/A Converter
  235. CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78054 Subseries)
  236. Serial Interface Channel 0 Functions
  237. Serial Bus Interface (SBI) System Configuration Example
  238. Serial Interface Channel 0 Configuration
  239. Serial Interface Channel 0 Block Diagram
  240. Serial Interface Channel 0 Control Registers
  241. Timer Clock Select Register 3 Format
  242. Serial Operating Mode Register 0 Format
  243. Serial Bus Interface Control Register Format
  244. Interrupt Timing Specify Register Format
  245. Serial Interface Channel 0 Operations
  246. wire serial I/O mode operation
  247. Wire Serial I/O Mode Timings
  248. Circuit of Switching in Transfer Bit Order
  249. SBI mode operation
  250. SBI Transfer Timings
  251. Bus Release Signal
  252. Addresses
  253. Commands
  254. Acknowledge Signal
  255. BUSY and READY Signals
  256. RELT, CMDT, RELD, and CMDD Operations (Master)
  257. ACKT Operation
  258. ACKE Operations
  259. ACKD Operations
  260. Various Signals in SBI Mode
  261. Pin Configuration
  262. Address Transmission from Master Device to Slave Device (WUP = 1)
  263. Command Transmission from Master Device to Slave Device
  264. Data Transmission from Master Device to Slave Device
  265. Data Transmission from Slave Device to Master Device
  266. Serial Bus Configuration Example Using 2-Wire Serial I/O Mode
  268. RELT and CMDT Operations
  269. SCK0/P27 pin output manipulation
  270. CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries)
  274. Serial Interface Channel 0 Interrupt Request Signal Generation
  280. Operation stop mode
  287. Start Condition
  288. Stop Condition
  289. Wait Signal
  291. Data Transmission from Master to Slave (Both Master and Slave Selected 9-Clock Wait)
  292. Data Transmission from Slave to Master (Both Master and Slave Selected 9-Clock Wait)
  293. Start Condition Output
  294. Slave Wait Release (Transmission)
  295. Slave Wait Release (Reception)
  296. SCK0/SCL/P27 pin output manipulation
  297. Logic Circuit of SCL Signal
  298. CHAPTER 18 SERIAL INTERFACE CHANNEL 1
  299. Serial Interface Channel 1 Configuration
  300. Serial Interface Channel 1 Block Diagram
  301. Serial Interface Channel 1 Control Registers
  303. Serial Operation Mode Register 1 Format
  304. Automatic Data Transmit/Receive Control Register Format
  305. Automatic Data Transmit/Receive Interval Specify Register Format
  306. Serial Interface Channel 1 Operations
  310. wire serial I/O mode operation with automatic transmit/receive function
  311. Basic Transmission/Reception Mode Operation Timings
  312. Basic Transmission/Reception Mode Flowchart
  313. Basic Transmission Mode Operation Timings
  314. Basic Transmission Mode Flowchart
  315. Repeat Transmission Mode Operation Timing
  316. Repeat Transmission Mode Flowchart
  317. Automatic Transmission/Reception Suspension and Restart
  318. System Configuration When the Busy Control Option is Used
  319. Operation Timings when Using Busy Control Option (BUSY0 = 0)
  320. Busy Signal and Wait Cancel (when BUSY0 = 0)
  321. Operation Timings when Using Busy & Strobe Control Option (BUSY0 = 0)
  322. Automatic Data Transmit/Receive Interval
  323. Operation Timing with Automatic Data Transmit/Receive Function Performed by Internal Clock
  324. Interval Timing Through CPU Processing (when the external clock is operating)
  325. CHAPTER 19 SERIAL INTERFACE CHANNEL 2
  326. Serial Interface Channel 2 Configuration
  327. Serial Interface Channel 2 Block Diagram
  328. Baud Rate Generator Block Diagram
  329. Serial Interface Channel 2 Control Registers
  330. Asynchronous Serial Interface Mode Register Format
  331. Serial Interface Channel 2 Operating Mode Settings
  332. Asynchronous Serial Interface Status Register Format
  333. Baud Rate Generator Control Register Format
  334. Relation between Main System Clock and Baud Rate
  335. Serial Interface Channel 2 Operation
  336. Asynchronous serial interface (UART) mode
  338. Relation between ASCK Pin Input Frequency and Baud Rate (When BRGC is set to 00H)
  339. Asynchronous Serial Interface Transmit/Receive Data Format
  340. Asynchronous Serial Interface Transmission Completion Interrupt Request Generation Timing
  341. Receive Error Timing
  342. wire serial I/O mode
  343. Wire Serial I/O Mode Timing
  345. Limitations when UART mode is used
  346. Receive Buffer Register Read Disable Period
  347. CHAPTER 20 REAL-TIME OUTPUT PORT
  348. Real-Time Output Port Configuration
  349. Real-time Output Buffer Register Configuration
  350. Real-Time Output Port Control Registers
  351. Real-time Output Port Control Register Format
  352. CHAPTER 21 INTERRUPT AND TEST FUNCTIONS
  353. Interrupt Sources and Configuration
  354. Basic Configuration of Interrupt Function
  355. Interrupt Function Control Registers
  356. Interrupt Request Flag Register Format
  357. Interrupt Mask Flag Register Format
  358. Priority Specify Flag Register Format
  362. Noise Eliminator Input/Output Timing (during rising edge detection)
  363. Program Status Word Configuration
  364. Interrupt Servicing Operations
  365. Flowchart of Generation from Non-Maskable Interrupt Request to Acknowledgment
  366. Non-Maskable Interrupt Request Acknowledge Operation
  367. Maskable interrupt request acknowledge operation
  368. Interrupt Request Acknowledge Processing Algorithm
  369. Interrupt Request Acknowledge Timing (Minimum Time)
  370. Software interrupt request acknowledge operation
  371. Multiple Interrupt Example
  372. Interrupt request reserve
  373. Test Functions
  374. Format of Interrupt Request Flag Register 1L
  375. Test input signal acknowledge operation
  376. CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION
  377. Memory Map when Using External Device Expansion Function
  378. External Device Expansion Function Control Register
  379. Memory Size Switching Register Format
  380. External Device Expansion Function Timing
  381. Instruction Fetch from External Memory
  382. External Memory Read Timing
  383. External Memory Write Timing
  384. External Memory Read Modify Write Timing
  385. Example of Connection with Memory
  386. CHAPTER 23 STANDBY FUNCTION
  387. Standby function control register
  388. Standby Function Operations
  389. HALT Mode Clear upon Interrupt Request Generation
  390. HALT Mode Release by RESET Input
  391. STOP mode
  392. STOP Mode Release by Interrupt Request Generation
  393. Release by STOP Mode RESET Input
  394. CHAPTER 24 RESET FUNCTION
  395. Timing of Reset Input by RESET Input
  396. Hardware Status after Reset
  397. CHAPTER 25 ROM CORRECTION
  398. Correction Address Registers 0 and 1 Format
  399. ROM Correction Control Registers
  400. ROM Correction Application
  401. Initialization Routine
  402. ROM Correction Operation
  403. ROM Correction Example
  404. Program Execution Flow
  405. Program Transition Diagram (when two places are corrected)
  406. Cautions on ROM Correction
  407. CHAPTER 26 PD78P054, 78P058
  408. Differences between PD78P054 and 78P058
  409. Memory Size Switching Register ( PD78P054)
  410. Memory Size Switching Register ( PD78P058)
  411. Internal Expansion RAM Size Switching Register
  412. PROM Programming
  413. PROM write procedure
  414. Page Program Mode Timing
  415. Byte Program Mode Flowchart
  416. Byte Program Mode Timing
  417. PROM reading procedure
  418. Erasure Procedure ( PD78P054KK-T and 78P058KK-T Only)
  419. CHAPTER 27 INSTRUCTION SET
  420. Legends Used in Operation List
  421. Description of "operation" column
  422. Operation List
  423. Instructions Listed by Addressing Type
  424. APPENDIX A DIFFERENCES BETWEEN PD78054, 78054Y SUBSERIES AND PD78058F, 78058FY SUBSERIES
  425. A-1. Major differences between PD78054, 78054Y Subseries and PD78058F, 78058FY Subseries
  426. APPENDIX B DEVELOPMENT TOOLS
  427. B-1. Development Tool Configuration
  428. B.1 Language Processing Software
  429. B.2 PROM Writing Tools
  430. B.3 Debugging Tools
  431. B.3.2 Software
  432. B.5 Upgrading Former In-circuit Emulators for 78K/0 Series to IE-78001-R-A
  433. B-2. EV-9200GC-80 Drawing (For Reference Only)
  434. B-3. EV-9200GC-80 Footprint (For Reference Only)
  435. B-4. TGK-080SDW Drawing (For Reference) (unit: mm)
  436. APPENDIX C EMBEDDED SOFTWARE
  437. APPENDIX D REGISTER INDEX
  438. APPENDIX E REVISION HISTORY
NEC PD78052 User Manual Manual pdf 105 page image
105CHAPTER 5 CPU ARCHITECTUREFigure 5-13. Data Memory Addressing (μPD78055, 78055Y)0000HGeneral Registers32 × 8 bitsInternal ROM40960 × 8 bitsInternal Buffer RAM32 × 8 bitsExternal Memory23168 × 8 bitsReservedA000H9FFFHFA80HFA7FHFAC0HFABFHFAE0HFADFHFEE0HFEDFHFF00HFEFFHFFFFHInternal High-speed RAM1024 × 8 bitsReservedFB00HFAFFHFF20HFF1FHFE20HFE1FHSpecial FunctionRegisters (SFRs)256 × 8 bits SFR AddressingRegister Addressing Short DirectAddressingDirect AddressingRegister IndirectAddressingBased AddressingBased IndexedAddressing
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This manual is suitable for:
PD78052PD78052(A)PD78052YPD78053PD78053(A)PD78053YPD78054PD78054(A)PD78054YPD78055PD78055YPD78056PD78056YPD78058PD78058YPD78P054PD78P058PD78P058YuPD78052uPD78052(A)uPD78052YuPD78053uPD78053(A)uPD78053YuPD78054uPD78054(A)uPD78054YuPD78055uPD78055YuPD78056uPD78056YuPD78058uPD78058YuPD78P054uPD78P058
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