345CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (μPD78054Y Subseries)Figure 17-2. Serial Interface Channel 0 Block DiagramRemark Output Control selects between CMOS output and N-ch open drain output.CSIE0 COI WUP CSIM04CSIM03CSIM02CSIM01CSIM00Serial Operating Mode Register 0ControlCircuitOutputControlSelectorSI0/SB0/SDA0/P25PM25OutputControlSO0/SB1/SDA1/P26 PM26OutputControlSCK0/SCL/P27PM27SelectorP25Output LatchP26 Output LatchCLDP27Output LatchInternal BusBSYE ACKD ACKE ACKT CMDD RELD CMDT RELTInternal BusStop Condition/Start Condition/AcknowledgeDetectorSerial ClockCounterSerial ClockControl CircuitCLRDSETQMatchAcknowledgeOutput CircuitInterruptRequestSignalGeneratorACKDCMDDRELDWUPSelector SelectorTCL33 TCL32 TCL31 TCL304Timer ClockSelectRegister 3f xx/2-fxx/28INTCSI0CLD SIC SVAMBSYECLC WREL WAT1 WAT0CSIM01CSIM00TO21/16DividerCSIM01CSIM00Interrupt TimingSpecify RegisterSlave AddressRegister (SVA)SVAMSerial Bus InterfaceControl Register2Serial I/O ShiftRegister 0 (SIO0)
