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NEC PD78E9860A manuals

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PD78E9860A

Brand: NEC | Category: Microcontrollers
Table of contents
  1. User's Manual U14826EJ5V0UD
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. Table Of Contents
  8. Table Of Contents
  9. Table Of Contents
  10. Table Of Contents
  11. Table Of Contents
  12. Table Of Contents
  13. Features
  14. Quality Grade
  15. K/0S Series Lineup
  16. Block Diagram
  17. Overview of Functions
  18. Pin Configuration (Top View)
  19. CHAPTER 3 PIN FUNCTIONS
  20. Description of Pin Functions
  21. IC (mask ROM version only)
  22. Pin I/O Circuits and Recommended Connection of Unused Pins
  23. CHAPTER 4 CPU ARCHITECTURE
  24. Internal program memory space
  25. Special function register (SFR) area
  26. Processor Registers
  27. Stack Pointer Configuration
  28. General-purpose registers
  29. Special function registers (SFRs)
  30. Special Function Registers
  31. Instruction Address Addressing
  32. Immediate addressing
  33. Register addressing
  34. Operand Address Addressing
  35. Short direct addressing
  36. Special function register (SFR) addressing
  37. Register indirect addressing
  38. Based addressing
  39. CHAPTER 5 EEPROM (DATA MEMORY)
  40. Format of EEPROM Write Control Register 10
  41. Notes for EEPROM Writing
  42. CHAPTER 6 PORT FUNCTIONS
  43. Port 0
  44. Port 2
  45. Port 4
  46. Port Function Control Registers
  47. Operation of Port Functions
  48. Clock Generator Functions
  49. Clock Generator Control Register
  50. System Clock Oscillators
  51. Examples of incorrect resonator connection
  52. Frequency divider
  53. Clock Generator Operation
  54. Changing Setting of CPU Clock
  55. CHAPTER 9 8-BIT TIMERS 30 AND 40
  56. Bit Timers 30, 40 Configuration
  57. Timer 30 Block Diagram
  58. Timer 40 Block Diagram
  59. Bit Timers 30, 40 Control Registers
  60. Format of 8-Bit Timer Mode Control Register 30
  61. Format of 8-Bit Timer Mode Control Register 40
  62. Format of Carrier Generator Output Control Register 40
  63. Format of Port Mode Register 2
  64. Bit Timers 30, 40 Operation
  65. Timing of Interval Timer Operation with 8-Bit Resolution (Basic Operation)
  66. Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Is Set to FFH)
  67. Timing of Interval Timer Operation with 8-Bit Resolution (When Timer 40 Match Signal Is Selected for Timer 30 Count Clock)
  68. Timing of Operation of External Event Counter with 8-Bit Resolution
  69. Timing of Square-Wave Output with 8-Bit Resolution
  70. Operation as 16-bit timer counter
  71. Timing of Interval Timer Operation with 16-Bit Resolution
  72. Timing of External Event Counter Operation with 16-Bit Resolution
  73. Timing of Square-Wave Output with 16-Bit Resolution
  74. Operation as carrier generator
  75. Timing of Carrier Generator Operation (When CR40 = N, CRH40 = M (M > N))
  76. Timing of Carrier Generator Operation (When CR40 = N, CRH40 = M (M < N))
  77. Timing of Carrier Generator Operation (When CR40 = CRH40 = N)
  78. Operation as PWM output (timer 40 only)
  79. PWM Output Mode Timing (Basic Operation)
  80. Notes on Using 8-Bit Timers 30, 40
  81. Counting Operation if Timer Is Started When TMI Is High
  82. CHAPTER 10 WATCHDOG TIMER
  83. Watchdog Timer Configuration
  84. Watchdog Timer Control Registers
  85. Format of Watchdog Timer Mode Register
  86. Watchdog Timer Operation
  87. Operation as interval timer
  88. CHAPTER 11 POWER-ON-CLEAR CIRCUITS
  89. Block Diagram of Power-on-Clear Circuit
  90. Power-on-Clear Circuit Control Registers
  91. Format of Low-Voltage Detection Register 1
  92. Power-on-Clear Circuit Operation
  93. Timing of Internal Reset Signal Generation When POC Circuit Normally Halted
  94. Operation of low-voltage detection (LVI) circuit
  95. LVI Circuit Operation Timing
  96. CHAPTER 12 BIT SEQUENTIAL BUFFER
  97. Bit Sequential Buffer Control Register
  98. Bit Sequential Buffer Operation
  99. CHAPTER 13 KEY RETURN CIRCUIT
  100. CHAPTER 14 INTERRUPT FUNCTIONS
  101. Interrupt Sources and Configuration
  102. Basic Configuration of Interrupt Function
  103. Interrupt Function Control Registers
  104. Format of Interrupt Mask Flag Register 0
  105. Interrupt Servicing Operation
  106. Flowchart from Non-Maskable Interrupt Request Generation to Acknowledgment (INTWDT)
  107. Maskable interrupt request acknowledgment operation
  108. Interrupt Request Acknowledgment Processing Algorithm
  109. Interrupt Request Acknowledgment Timing (When Interrupt Request Flag Is Set at Last Clock During Instruction Execution)
  110. Multiple interrupt servicing
  111. Interrupt request pending
  112. CHAPTER 15 STANDBY FUNCTION
  113. Standby function control register
  114. Standby Function Operation
  115. Releasing HALT Mode by Interrupt
  116. Releasing HALT Mode by RESET Input
  117. STOP mode
  118. Releasing STOP Mode by Interrupt
  119. Releasing STOP Mode by RESET Input
  120. CHAPTER 16 RESET FUNCTION
  121. Reset Timing by RESET Input
  122. Status of Hardware After Reset
  123. CHAPTER 17 µ PD78E9860A, 78E9861A
  124. EEPROM Features (Program Memory)
  125. Communication mode
  126. Example of Connection with Dedicated Flash Programmer
  127. Pin Connection List
  128. On-board pin processing
  129. Signal Conflict (Input Pin of Serial Interface)
  130. Signal Conflict (RESET Pin)
  131. Connection of adapter for EEPROM writing
  132. CHAPTER 18 MASK OPTIONS
  133. CHAPTER 19 INSTRUCTION SET OVERVIEW
  134. Description of "Operation" column
  135. Operation List
  136. Instructions Listed by Addressing Type
  137. CHAPTER 20 ELECTRICAL SPECIFICATIONS
  138. CHAPTER 22 PACKAGE DRAWING
  139. CHAPTER 23 RECOMMENDED SOLDERING CONDITIONS
  140. APPENDIX A DEVELOPMENT TOOLS
  141. A-1 Development Tools
  142. A.1 Software Package
  143. A.3 Control Software
  144. A.5 Debugging Tools (Hardware)
  145. A.6 Debugging Tools (Software)
  146. APPENDIX B NOTES ON TARGET SYSTEM DESIGN
  147. APPENDIX C REGISTER INDEX
  148. C.2 Register Symbol Index (in Alphabetical Order)
  149. APPENDIX D REVISION HISTORY
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