Contents - Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- DAQ-STC Applications
- Analog Output Application
- DAQ-STC Block Diagram
- Overview
- Features
- Simplified Model
- Figure 2-2. AITM Simplified Model
- Analog Input Functions
- ADC Control
- Figure 2-4. Configuration FIFO Control
- CONVERT Timing
- Figure 2-6. Internal CONVERT Timing
- Scan-Level Timing and Control
- External START Mode
- Figure 2-9. External START
- Acquisition-Level Timing and Control
- Continuous Acquisition Mode
- Staged Acquisition
- Free-Run Gating Mode
- Single-Wire Mode
- Pin Locator Interface
- Programming Information
- Windowing Registers
- Resetting
- Board Power-up Initialization
- Initialize Configuration Memory Output
- Board Environment Setup
- FIFO Request
- Software Gate Operation
- Trigger Signals
- Number of Scans
- Start of Scan
- End of Scan
- Convert Signal
- Enable Interrupts
- Arming
- Analog Input Program
- Change Scan Rate during an Acquisition
- Master/Slave Operation Considerations
- Analog Input-Related Interrupts
- Bitfield Descriptions
- Timing Diagrams
- OUT_CLK
- Basic Analog Input Timing
- Data FIFOs
- Configuration Memory
- Table 2-4. Configuration Memory Timing
- Maximum Rate Analog Input
- External CONVERT Source
- External Triggers
- Figure 2-21. External Trigger Timing, Asynchronous Level
- Figure 2-23. External Trigger Timing, Synchronous Level Internal CONVERT Mode
- Figure 2-25. External Trigger Timing, Synchronous Level External CONVERT Mode
- Trigger Output
- Figure 2-27. START1 Delays, Synchronous Mode, Internal CONVERT
- Figure 2-30. START2 Delays, Synchronous Mode, External CONVERT
- START Trigger and SCAN_IN_PROG Assertion
- Figure 2-33. START Delays, Internal CONVERT
- Figure 2-34. START Delays, External CONVERT
- SCAN_IN_PROG Deassertion
- Figure 2-36. STOP Delay, Synchronous Mode
- Counter Outputs
- Macro-Level Analog Input Timing
- Table 2-8. Interval Scanning Mode Timing
- External Gating
- Figure 2-43. Free-Run Gating Mode Timing, External CONVERT
- Figure 2-44. Halt-Gating Mode Timing, Internal CONVERT
- Detailed Description
- Internal Signals and Operation
- Trigger Selection and Conditioning
- Figure 2-46. START and STOP Routing Logic
- Figure 2-48. EXT_GATE Routing Logic
- Using Edge Detection
- Analog Input Counters
- SC Counter
- Figure 2-49. SC Control Circuit State Transitions
- SI Counter
- SI2 Counter
- DIV Counter
- DIV Control
- Interrupt Control
- Table 2-11. Analog Input Interrupts
- Error Detection
- Nominal Signal Pulsewidths
- Programming the AOTM
- Analog Output Functions
- Figure 3-2. DAQ-STC-Driven Analog Output
- Figure 3-3. CPU-Driven Analog Output
- DAC Interface
- Figure 3-5. FIFO Data Interface
- Serial Link Data Interface
- Unbuffered Data Interface
- External UPDATE
- Single-Buffer Mode
- Waveform Staging
- Mute Buffers
- Secondary Analog Output
- Programming for a Primary Analog Output Operation
- Number of Buffers
- Update Selection
- Channel Select
- LDAC Source and UPDATE Mode
- Starting the Waveform
- Waveform Staging for Primary Analog Output
- Changing Update Rate during an Output Operation for Primary Analog Output Group
- Master/Slave Operation Considerations for Primary Analog Output Group
- Programming for a Secondary Analog Output Group Operation
- Waveform Staging for Secondary Analog Output
- Changing Update Rate during an Output Operation for Secondary Analog Output
- Master/Slave Operation Considerations for Secondary Analog Output
- Signal Definitions
- UPDATE_SRC
- Figure 3-14. DAQ-STC-Driven Analog Output Timing
- CPU-Driven Analog Output Timing
- Figure 3-15. CPU-Driven Analog Output Timing
- DAQ-STC- and CPU-Driven Analog Output Timing
- Figure 3-16. Analog Output Contention Timing, Case A
- Figure 3-17. Analog Output Contention Timing, Case B
- Secondary Analog Output Timing
- Decoded Signal Timing
- Figure 3-19. Decoded Signal Timing
- Local Buffer Mode Timing
- Figure 3-20. Local Buffer Mode Timing
- Unbuffered Data Interface Timing
- Figure 3-21. Unbuffered Data Interface Timing
- Maximum Update Rate Timing
- External Trigger Timing
- Figure 3-25. External Trigger, Synchronous Level, Internal UPDATE Mode
- Figure 3-29. START1 Delays, Synchronous Mode, Internal UPDATE
- Figure 3-30. START1 Delays, Synchronous Mode, External UPDATE
- UC_TC
- Figure 3-35. START1 Routing Logic
- Analog Output Counters
- UI Control
- UC Control
- BC Counter
- UI2 Counter
- Output Control
- Counter/Timer Functions
- Figure 4-2. Simple Event Counting
- Figure 4-4. Buffered Noncumulative Event Counting
- Time Measurement
- Figure 4-7. Single-Period Measurement
- Figure 4-9. Buffered Period Measurement
- Pulse Generation
- Figure 4-12. Single Pulse Generation
- Figure 4-14. Retriggerable Single Pulse Generation
- Pulse-Train Generation
- Figure 4-16. Continuous Pulse-Train Generation
- Figure 4-18. Buffered Pulse-Train Generation
- Figure 4-19. Frequency Shift Keying
- Pin Interface
- Notation
- Simple Event Counting
- Buffered Event Counting
- Relative Position Sensing
- Single-Period and Pulsewidth Measurement
- Buffered Period, Semiperiod, and Pulsewidth Measurement
- Pulse and Continuous Pulse-Train Generation
- Frequency Shift Keying
- Pulse-Train Generation for ETS
- Reading the Counter Contents
- Enabling the General Purpose Counter/Timer Output Pin
- Table 4-2. CTRGATE Reference Pin Selection
- CTRSRC Minimum Period and Minimum Pulsewidth
- G_GATE Minimum Pulsewidth
- CTRGATE to CTROUT Delay
- CTRGATE Setup
- CTR_U/D Setup
- Figure 4-28. CTR_U/D Setup Timing, Internal Timing Mode
- G_SOURCE Selection and Conditioning
- G_GATE Selection and Conditioning
- G_OUT Conditioning and Routing
- Table 4-12. G_OUT0/RTSI_IO Selection
- G_CONTROL Conditioning
- START/STOP on G_CONTROL
- UP/DOWN on G_CONTROL
- Detailed Operation by Application
- Figure 4-32. Simple Event Counting
- Figure 4-34. Buffered Noncumulative-Event Counting
- Figure 4-35. Buffered Cumulative-Event Counting
- Figure 4-37. Single-Period Measurement
- Figure 4-38. Single Pulsewidth Measurement
- Figure 4-39. Buffered Period Measurement
- Figure 4-40. Buffered Semiperiod Measurement
- Figure 4-41. Buffered Pulsewidth Measurement
- Figure 4-42. Single Pulse Generation
- Figure 4-43. Single-Triggered Pulse Generation
- Figure 4-44. Retriggerable Single Pulse Generation
- Figure 4-45. Continuous Pulse-Train Generation
- Figure 4-46. Buffered Pulse-Train Generation
- Figure 4-47. Frequency Shift Keying
- Figure 4-48. Pulse Generation for ETS
- Table 5-3. PFI<0..9> Output Selections
- Table 6-3. RTSI_BRD<0..1> Output Selections
- Overview of DIO Functions
- Parallel Input
- Serial Mode
- Serial I/O
- Programming the Digital Interface
- Parallel Digital I/O
- Hardware-Controlled Serial Digital I/O
- Software-Controlled Serial Digital I/O
- Serial Output Timing
- Interrupt Handling
- Interrupt Conditions
- Table 9-1. Pin Interface
- Programming the Write Strobes
- Figure 9-1. Intel Bus Interface Read Timing
- Figure 9-3. Motorola Bus Interface Read Timing
- Figure 9-4. Motorola Bus Interface Write Timing
- Clock Distribution
- Frequency Output
- Figure 10-2. Low-Window Mode
- Figure 10-4. Middle-Window Mode
- Test Mode
- Figure 10-7. Test Mode Internal Gate Tree
- Table 10-2. Test Mode Input Pin Pairs
- Programming FOUT
- Table B-1. DAQ-STC Registers
- Table B-2. Registers in Order of Address*
- Table B-3. Bitfield Description Guide
- Table C-1. DAQ-STC Pins in Alphabetical Order
- Table C-2. Summary of Buffer Types
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ContentsDAQ-STC Technical Reference Manualxx ©National Instruments CorporationTable 4-1. CTRSRC Reference Pin Selection........................................................ 4-53Table 4-2. CTRGATE Reference Pin Selection .................................................... 4-54Table 4-3. CTR_U/D Reference Pin Selection ...................................................... 4-54Table 4-4. Internal Signal Description .................................................................. 4-62Table 4-5. G_SOURCE Selection .......................................................................... 4-63Table 4-6. G_SOURCE Conditioning.................................................................... 4-63Table 4-7. G_GATE Selection ............................................................................... 4-64Table 4-8. G_GATE Conditioning ......................................................................... 4-64Table 4-9. G_UP_DOWN Modes ......................................................................... 4-65Table 4-10. G_OUT Mode ....................................................................................... 4-65Table 4-11. G_OUT Polarity.................................................................................... 4-65Table 4-12. G_OUT0/RTSI_IO Selection................................................................ 4-66Table 4-13. G_OUT1/DIV_TC_OUT Selection ...................................................... 4-66Table 4-14. G_CONTROL Conditioning................................................................. 4-67Table 4-15. Gate Actions ......................................................................................... 4-67Table 4-16. START/STOP Modes for Edge Gating ................................................ 4-68Table 4-17. Reload on G_CONTROL Selections ................................................... 4-68Table 4-18. Gate Interrupts ...................................................................................... 4-69Table 4-19. PFI Selectors ......................................................................................... 4-70Table 5-1. Pin Interface ......................................................................................... 5-2Table 5-2. PFI<0..9> Input Selections .................................................................. 5-7Table 5-3. PFI<0..9> Output Selections................................................................. 5-8Table 6-1. Pin Interface .......................................................................................... 6-2Table 6-2. RTSI_TRIGGER<0..6> Output Selections........................................... 6-6Table 6-3. RTSI_BRD<0..1> Output Selections.................................................... 6-7Table 6-4. RTSI_BRD<2..3> Output Selections.................................................... 6-7Table 7-1. Pin Interface ......................................................................................... 7-6Table 7-2. Serial Output Source Select .................................................................. 7-17Table 8-1. Pin Interface .......................................................................................... 8-2Table 8-2. Interrupt Condition Summary .............................................................. 8-15Table 9-1. Pin Interface ......................................................................................... 9-2Table 9-2. Intel Bus Interface Timing ................................................................... 9-6Table 9-3. Intel Bus Interface Timing .................................................................... 9-8Table 10-1. Timebases Derived from IN_TIMEBASE ........................................... 10-2Table 10-2. Test Mode Input Pin Pairs .................................................................... 10-8Table 10-3. Pin Interface ......................................................................................... 10-9
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