Chapter 2 Analog Input Timing/Control©National Instruments Corporation2-5DAQ-STC Technical Reference ManualFigure 2-2 shows a simplified model of the AITM module.Figure 2-2. AITM Simplified ModelOne of the primary features of the AITM is that a wide variety of signals can be selected astiming and control sources. The simplified model depicts this as a select circuit, whichchooses between the 10 PFI signals PFI<0..9>, the seven RTSI signalsRTSI_TRIGGER<0..6>, and the dedicated STOP input signal AI_STOP_IN. Many of thesignals required for the ADC can come from external sources routed through the selector. TheDAQ-STC can also generate the timing sources internally.The simplified model in Figure 2-2 shows that the source for the CONVERT pulse may comefrom the SI2 counter (internal CONVERT source) or the select circuit (external CONVERTsource). SOC (start of conversion) and EOC (end of conversion) are status signals generatedby the ADC. SOC indicates that a conversion has begun and EOC indicates that a conversionis complete.Using CONVERT as a reference, the output circuit generates several ancillary signals usedon the board. The LOCALMUX_CLK (configuration FIFO advance) signal, which pulsesafter an integral number of CONVERTs, advances the configuration FIFO to the next inputchannel. The LOCALMUX_FFRT (configuration FIFO retransmit) signal, which pulseswhen the configuration FIFO empties, refills the configuration FIFO. The EXTMUX_CLK(external multiplexer clock) signal, which pulses on every CONVERT, advances the channelmultiplexer. The SHIFTIN signals (AI_FIFO_SHIFTIN and SHIFTIN), which pulse after theADC has completed a conversion, move the data into the analog input data FIFO. TheAIFREQ (AI data FIFO request) signal generates a DMA request based on the analog inputPFI<0..9>RTSI_TRIGGER<0..6>AI_STOP_INSOCEOCGHOSTAIFFFAIFHFAIFEFSELECTCONTROLSTOPSTARTSTART1SC_TCSI2_TCSI_TCDIV_TCSI2COUNTERSICOUNTERDIVCOUNTERSCCOUNTEROUTPUTCONVERTAI_FIFO_SHIFTINSHIFTINLOCALMUX_CLKLOCALMUX_FFRTEXTMUX_CLKSCAN_IN_PROGAIFREQ
