Contents - Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- DAQ-STC Applications
- Analog Output Application
- DAQ-STC Block Diagram
- Overview
- Features
- Simplified Model
- Figure 2-2. AITM Simplified Model
- Analog Input Functions
- ADC Control
- Figure 2-4. Configuration FIFO Control
- CONVERT Timing
- Figure 2-6. Internal CONVERT Timing
- Scan-Level Timing and Control
- External START Mode
- Figure 2-9. External START
- Acquisition-Level Timing and Control
- Continuous Acquisition Mode
- Staged Acquisition
- Free-Run Gating Mode
- Single-Wire Mode
- Pin Locator Interface
- Programming Information
- Windowing Registers
- Resetting
- Board Power-up Initialization
- Initialize Configuration Memory Output
- Board Environment Setup
- FIFO Request
- Software Gate Operation
- Trigger Signals
- Number of Scans
- Start of Scan
- End of Scan
- Convert Signal
- Enable Interrupts
- Arming
- Analog Input Program
- Change Scan Rate during an Acquisition
- Master/Slave Operation Considerations
- Analog Input-Related Interrupts
- Bitfield Descriptions
- Timing Diagrams
- OUT_CLK
- Basic Analog Input Timing
- Data FIFOs
- Configuration Memory
- Table 2-4. Configuration Memory Timing
- Maximum Rate Analog Input
- External CONVERT Source
- External Triggers
- Figure 2-21. External Trigger Timing, Asynchronous Level
- Figure 2-23. External Trigger Timing, Synchronous Level Internal CONVERT Mode
- Figure 2-25. External Trigger Timing, Synchronous Level External CONVERT Mode
- Trigger Output
- Figure 2-27. START1 Delays, Synchronous Mode, Internal CONVERT
- Figure 2-30. START2 Delays, Synchronous Mode, External CONVERT
- START Trigger and SCAN_IN_PROG Assertion
- Figure 2-33. START Delays, Internal CONVERT
- Figure 2-34. START Delays, External CONVERT
- SCAN_IN_PROG Deassertion
- Figure 2-36. STOP Delay, Synchronous Mode
- Counter Outputs
- Macro-Level Analog Input Timing
- Table 2-8. Interval Scanning Mode Timing
- External Gating
- Figure 2-43. Free-Run Gating Mode Timing, External CONVERT
- Figure 2-44. Halt-Gating Mode Timing, Internal CONVERT
- Detailed Description
- Internal Signals and Operation
- Trigger Selection and Conditioning
- Figure 2-46. START and STOP Routing Logic
- Figure 2-48. EXT_GATE Routing Logic
- Using Edge Detection
- Analog Input Counters
- SC Counter
- Figure 2-49. SC Control Circuit State Transitions
- SI Counter
- SI2 Counter
- DIV Counter
- DIV Control
- Interrupt Control
- Table 2-11. Analog Input Interrupts
- Error Detection
- Nominal Signal Pulsewidths
- Programming the AOTM
- Analog Output Functions
- Figure 3-2. DAQ-STC-Driven Analog Output
- Figure 3-3. CPU-Driven Analog Output
- DAC Interface
- Figure 3-5. FIFO Data Interface
- Serial Link Data Interface
- Unbuffered Data Interface
- External UPDATE
- Single-Buffer Mode
- Waveform Staging
- Mute Buffers
- Secondary Analog Output
- Programming for a Primary Analog Output Operation
- Number of Buffers
- Update Selection
- Channel Select
- LDAC Source and UPDATE Mode
- Starting the Waveform
- Waveform Staging for Primary Analog Output
- Changing Update Rate during an Output Operation for Primary Analog Output Group
- Master/Slave Operation Considerations for Primary Analog Output Group
- Programming for a Secondary Analog Output Group Operation
- Waveform Staging for Secondary Analog Output
- Changing Update Rate during an Output Operation for Secondary Analog Output
- Master/Slave Operation Considerations for Secondary Analog Output
- Signal Definitions
- UPDATE_SRC
- Figure 3-14. DAQ-STC-Driven Analog Output Timing
- CPU-Driven Analog Output Timing
- Figure 3-15. CPU-Driven Analog Output Timing
- DAQ-STC- and CPU-Driven Analog Output Timing
- Figure 3-16. Analog Output Contention Timing, Case A
- Figure 3-17. Analog Output Contention Timing, Case B
- Secondary Analog Output Timing
- Decoded Signal Timing
- Figure 3-19. Decoded Signal Timing
- Local Buffer Mode Timing
- Figure 3-20. Local Buffer Mode Timing
- Unbuffered Data Interface Timing
- Figure 3-21. Unbuffered Data Interface Timing
- Maximum Update Rate Timing
- External Trigger Timing
- Figure 3-25. External Trigger, Synchronous Level, Internal UPDATE Mode
- Figure 3-29. START1 Delays, Synchronous Mode, Internal UPDATE
- Figure 3-30. START1 Delays, Synchronous Mode, External UPDATE
- UC_TC
- Figure 3-35. START1 Routing Logic
- Analog Output Counters
- UI Control
- UC Control
- BC Counter
- UI2 Counter
- Output Control
- Counter/Timer Functions
- Figure 4-2. Simple Event Counting
- Figure 4-4. Buffered Noncumulative Event Counting
- Time Measurement
- Figure 4-7. Single-Period Measurement
- Figure 4-9. Buffered Period Measurement
- Pulse Generation
- Figure 4-12. Single Pulse Generation
- Figure 4-14. Retriggerable Single Pulse Generation
- Pulse-Train Generation
- Figure 4-16. Continuous Pulse-Train Generation
- Figure 4-18. Buffered Pulse-Train Generation
- Figure 4-19. Frequency Shift Keying
- Pin Interface
- Notation
- Simple Event Counting
- Buffered Event Counting
- Relative Position Sensing
- Single-Period and Pulsewidth Measurement
- Buffered Period, Semiperiod, and Pulsewidth Measurement
- Pulse and Continuous Pulse-Train Generation
- Frequency Shift Keying
- Pulse-Train Generation for ETS
- Reading the Counter Contents
- Enabling the General Purpose Counter/Timer Output Pin
- Table 4-2. CTRGATE Reference Pin Selection
- CTRSRC Minimum Period and Minimum Pulsewidth
- G_GATE Minimum Pulsewidth
- CTRGATE to CTROUT Delay
- CTRGATE Setup
- CTR_U/D Setup
- Figure 4-28. CTR_U/D Setup Timing, Internal Timing Mode
- G_SOURCE Selection and Conditioning
- G_GATE Selection and Conditioning
- G_OUT Conditioning and Routing
- Table 4-12. G_OUT0/RTSI_IO Selection
- G_CONTROL Conditioning
- START/STOP on G_CONTROL
- UP/DOWN on G_CONTROL
- Detailed Operation by Application
- Figure 4-32. Simple Event Counting
- Figure 4-34. Buffered Noncumulative-Event Counting
- Figure 4-35. Buffered Cumulative-Event Counting
- Figure 4-37. Single-Period Measurement
- Figure 4-38. Single Pulsewidth Measurement
- Figure 4-39. Buffered Period Measurement
- Figure 4-40. Buffered Semiperiod Measurement
- Figure 4-41. Buffered Pulsewidth Measurement
- Figure 4-42. Single Pulse Generation
- Figure 4-43. Single-Triggered Pulse Generation
- Figure 4-44. Retriggerable Single Pulse Generation
- Figure 4-45. Continuous Pulse-Train Generation
- Figure 4-46. Buffered Pulse-Train Generation
- Figure 4-47. Frequency Shift Keying
- Figure 4-48. Pulse Generation for ETS
- Table 5-3. PFI<0..9> Output Selections
- Table 6-3. RTSI_BRD<0..1> Output Selections
- Overview of DIO Functions
- Parallel Input
- Serial Mode
- Serial I/O
- Programming the Digital Interface
- Parallel Digital I/O
- Hardware-Controlled Serial Digital I/O
- Software-Controlled Serial Digital I/O
- Serial Output Timing
- Interrupt Handling
- Interrupt Conditions
- Table 9-1. Pin Interface
- Programming the Write Strobes
- Figure 9-1. Intel Bus Interface Read Timing
- Figure 9-3. Motorola Bus Interface Read Timing
- Figure 9-4. Motorola Bus Interface Write Timing
- Clock Distribution
- Frequency Output
- Figure 10-2. Low-Window Mode
- Figure 10-4. Middle-Window Mode
- Test Mode
- Figure 10-7. Test Mode Internal Gate Tree
- Table 10-2. Test Mode Input Pin Pairs
- Programming FOUT
- Table B-1. DAQ-STC Registers
- Table B-2. Registers in Order of Address*
- Table B-3. Bitfield Description Guide
- Table C-1. DAQ-STC Pins in Alphabetical Order
- Table C-2. Summary of Buffer Types
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ContentsDAQ-STC Technical Reference Manualviii ©National Instruments Corporation3.4.3 Data Interfaces ................................................................................... 3-83.4.3.1 FIFO Data Interface...................................................... 3-83.4.3.2 Serial Link Data Interface ............................................ 3-103.4.3.3 Unbuffered Data Interface ............................................ 3-113.4.4 Update Timing for Primary Group Analog Output............................ 3-113.4.4.1 Internal UPDATE......................................................... 3-113.4.4.2 External UPDATE........................................................ 3-123.4.5 Buffer Timing and Control for Primary Analog Output .................... 3-123.4.5.1 Single-Buffer Mode...................................................... 3-133.4.5.2 Continuous Mode ......................................................... 3-133.4.5.3 Waveform Staging........................................................ 3-143.4.5.4 Mute Buffers................................................................. 3-153.4.5.5 Master/Slave Trigger .................................................... 3-153.4.6 Secondary Analog Output .................................................................. 3-163.5 Pin Interface ....................................................................................................... 3-163.6 Programming Information ................................................................................. 3-203.6.1 Programming for a Primary Analog Output Operation ..................... 3-203.6.1.1 Overview ...................................................................... 3-213.6.1.2 Resetting ....................................................................... 3-213.6.1.3 Board Power-up Initialization ...................................... 3-223.6.1.4 Trigger Signals ............................................................. 3-233.6.1.5 Number of Buffers........................................................ 3-243.6.1.6 Update Selection........................................................... 3-263.6.1.7 Channel Select .............................................................. 3-283.6.1.8 LDAC Source and UPDATE Mode ............................. 3-293.6.1.9 Stop On Error ............................................................... 3-293.6.1.10 FIFO Mode ................................................................... 3-293.6.1.11 Enable Interrupts .......................................................... 3-303.6.1.12 Arming.......................................................................... 3-303.6.1.13 Starting the Waveform ................................................. 3-313.6.1.14 Primary Analog Output Program.................................. 3-313.6.2 Waveform Staging for Primary Analog Output ................................. 3-323.6.3 Changing Update Rate during an Output Operation forPrimary Analog Output Group........................................................ 3-343.6.4 Master/Slave Operation Considerations for Primary AnalogOutput Group .................................................................................. 3-353.6.5 Primary Analog Output Group-Related Interrupts............................. 3-353.6.6 Programming for a Secondary Analog Output Group Operation ...... 3-383.6.6.1 Overview ...................................................................... 3-383.6.6.2 Resetting ....................................................................... 3-383.6.6.3 Board Power-up Initialization ...................................... 3-393.6.6.4 Hardware Gate Programming....................................... 3-393.6.6.5 Software Gate Operation .............................................. 3-40
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