Chapter 3 Analog Output Timing/ControlDAQ-STC Technical Reference Manual3-120 ©National Instruments Corporation3.8.3.5 BC CounterThe BC counter is a 24-bit down counter with dual-load registers and output save latch. TheBC counter typically counts the number of buffers to be output. The bitfieldAO_BC_Source_Select controls the BC_SRC. The choices for BC source are UPDATEpulses or UC_TC pulses. Normally, the BC source is configured to count UC_TC pulses. Thecounter load registers are directly accessible from the register map. If the counter is disarmed,AO_BC_Load loads the counter with the value from the selected load register.During normal operation, the BC counter will synchronously reload from the selected loadregister following BC_TC. Two options—AO_BC_Reload_Mode andAO_BC_Switch_Load_On_TC—change the selected load register under various conditions.The options are to switch load registers on every BC_TC and to switch load registers on thenext BC_TC. The BC control circuit generates the count enable signals.The BC save register latch signal asserts after a rising and then a falling edge of BC_SRCfollowing a 1 being written to AO_BC_Save_Trace. The BC save register latch signaldeasserts after a rising, then a falling edge of BC_SRC following a zero being written toAO_BC_Save_Trace.3.8.3.6 BC ControlThe BC counter is controlled by a circuit whose state transitions are shown in Figure 3-39.The BC counter control circuit has two states—WAIT and CNT. On power up, the controlcircuit begins and remains in the WAIT state until the counter is armed and a START1 pulseis received. The control circuit then transitions to the CNT state and remains there until thecount termination condition is reached.The BC counter normally remains armed and retriggerable at the end of a waveformgeneration sequence. The BC counter has the option AO_Trigger_Once to disarm itself afterthe first BC_TC. At the end of a nonretriggerable waveform-generation sequence, the BC_TCmasks off the last UPDATE pulse to prevent an undesired output.
