Nuvoton NUC502ADN User Manual

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Nuvoton NUC502ADN User Manual Manual pdf 107 page image

NUC502Apr 30, 2015 Page 107 of 266 Rev 1.16.8 Advanced Interrupt Controller6.8.1 OverviewAn interrupt temporarily changes the execution sequence of a program to react to aparticular event such as power failure, watchdog timer timeout, and engine complete,system events, external event trigger and so on. The ARM processor provides two modes ofinterrupts, the Fast Interrupt (FIQ) mode for critical session and the Interrupt (IRQ)mode for general purpose. The IRQ exception mode is occurred when the NIRQ input isasserted. Similarly, the FIQ exception mode is occurred when the NFIQ input is asserted.The FIQ mode has privilege over the IRQ mode and can preempt an ongoing IRQ mode. It ispossible to ignore the NFIQ and the NIRQ by setting the F-bit and I-bit in the currentprogram status register (CPSR).The NUC502 incorporates the advanced interrupt controller (AIC) that is capable ofdealing with the interrupt requests from different sources. Each interrupt source is uniquelyassigned to an interrupt channel. For example, the watchdog timer interrupt is assigned tochannel 2. The AIC implements a proprietary eight-level priority scheme that differentiatesthe available interrupt sources into eight priority levels. Interrupt sources within the prioritylevel 0 have the highest priority and the priority level 7 has the lowest. To work this schemeproperly, you must specify a certain priority level to each interrupt source during power-oninitialization; otherwise, the system shall behave unexpectedly. Within each priority level,interrupt source that is positioned in a lower channel has a higher priority. Interrupt sourcethat is active, enabled, and positioned in the lowest channel within the priority level 0 ispromoted to the FIQ mode. Interrupt sources within the priority levels other than 0 canpetition for the IRQ mode. The IRQ mode can be preempted by the occurrence of the FIQmode. Interrupt nesting is performed automatically by the AIC. A higher priority interruptsource will cause the NIRQ to CPU be asserted again when CPU is servicing a lower priorityinterrupt if the I-bit in CPSR is enabled.Though interrupt sources originated from the NUC502 itself are intrinsically high-levelsensitive, the AIC can be configured as either low-level sensitive, high-level sensitive,negative-edge triggered, or positive-edge triggered to each interrupt source.6.8.2 Features AMBA APB bus interface and Individual mask for each interrupt source External interrupts can be programmed as either edge-triggered or level-sensitive External interrupts can be programmed as either low-active or high-active Has flags to reflect the status of each interrupt source Proprietary 8-level interrupt scheme to ease the burden from the interrupt Daisy-chain priority mechanism is applied to interrupts set as the same priority level. Automatically masking out the lower priority interrupt during interrupt nesting Automatically clearing the interrupt flag when the external interrupt source isprogrammed to be edge-triggered