Nuvoton NUC502ADN User Manual

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Nuvoton NUC502ADN User Manual Manual pdf 164 page image

NUC502Apr 30, 2015 Page 164 of 266 Rev 1.16.11 PWM-Timer6.11.1 IntroductionThere are 4 PWM-Timers enclosed. The 4 PWM-Timers has 2 Pre-scale, 2 clock divider,4 clock selectors, 4 16-bit counters, 4 16-bit comparators, 2 Dead-Zone generators. Theyare all driven by APB clock. Each can be used as a timer and issues interrupt independently.Each two PWM-Timers share the same pre-scale (0-1 share prescale0 and 2-3 shareprescale1). Clock divider provides each timer with 5 clock sources (1, 1/2, 1/4, 1/8, 1/16).Each timer receives its own clock signal from clock divider which receives clock from 8-bitpre-scale. The 16-bit counter in each timer receive clock signal from clock selector and canbe used to handle one PWM period. The 16-bit comparator compares number in counterwith threshold number in register loaded previously to generate PWM duty cycle.The clock signal from clock divider is called PWM clock. Dead-Zone generator utilizePWM clock as clock source. Once Dead-Zone generator is enabled, output of two PWM-Timers are blocked. Two output pin are all used as Dead-Zone generator output signal tocontrol off-chip power device. Dead-Zone generator 0 is used to control outputs of timer0&1, and Dead-Zone generator 1 is used to control outputs of timer 2&3.To prevent PWM driving output pin with unsteady waveform, 16-bit counter and 16-bitcomparator are implemented with double buffering feature. User can feel free to write datato counter buffer register and comparator buffer register without generating glitch.When 16-bit down counter reaches zero, the interrupt request is generated to informCPU that time is up. When counter reaches zero, if counter is set as toggle mode, it isreloaded automatically and start to generate next cycle. User can set counter as one-shotmode instead of toggle mode. If counter is set as one-shot mode, counter will stop andgenerate one interrupt request when it reaches zero.The value of comparator is used for pulse width modulation. The counter control logicchanges the output level when down-counter value matches the value of compare register.Each PWM-Timer includes a capture channel. The Capture 0 and PWM 0 share a timerthat included in PWM 0; and the Capture 1 and PWM 1 share another timer, and etc.Therefore user must setup the PWM-Timer before turn on Capture feature. Please referencethe section of PWM-Timer for more detail description of setup PWM-Timer. After enablingcapture feature, the capture always latched PWM-counter to CRLR when input channel has arising transition and latched PWM-counter to CFLR when input channel has a fallingtransition. Capture channel 0 interrupt is programmable by setting CCR0[1] (Rising latchInterrupt enable) and CCR0[2] (Falling latch Interrupt enable) to decide the condition ofinterrupt occur. Capture channel 1 has the same feature by setting CCR0[17] and CCR0[18].And capture channel 2 & 3 has the same feature by setting CCR1[1],CCR1[2] and CCR1[17],CCR1[18] respectively. Whenever Capture issues Interrupt 0/1/2/3, the PWM counter