Nuvoton NUC502ADN User Manual

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Nuvoton NUC502ADN User Manual Manual pdf 207 page image

NUC502Apr 30, 2015 Page 207 of 266 Rev 1.16.13 Serial Peripheral Interface Controller (SPIMaster/Slave)6.13.1 SPI Function Description and FeaturesThe SPI controller performs a serial-to-parallel conversion on data charactersreceived from the peripheral, and a parallel-to-serial conversion on data charactersreceived from CPU. This controller can drive up to 2 external peripherals, but is time-shared and can not operate simultaneously. It also can be driven as the slave devicewhen the CNTRL[18], SLAVE bit, be set.It can generate an interrupt signal when data transfer is finished and can be clearedby writing 1 to the interrupt flag. The active level of slave select signal can be chosen tolow active or high active on SSR[SS_LVL] bit, which depends on the peripheral it’sconnected. Writing a divisor into DIVIDER register can program the frequency of serialclock output. This controller contains four 32-bit transmit/receive buffers, and canprovide burst mode operation. It supports variable length transfer and the maximumtransmitted/received length can be up to 128 bits.The SPI Master/Slave Core includes the following features: AMBA APB interface compatible Support SPI master/slave mode Full duplex synchronous serial data transfer Variable length of transfer word up to 32 bits Provide burst mode operation, transmit/receive can be executed up to four times inone transfer MSB or LSB first data transfer Rx and Tx on both rising or falling edge of serial clock independently 2 slave/device select lines when it is as the master mode, and 1 slave/device selectline when it is as the slave mode Fully static synchronous design with one clock domain Only Support the external master device that the frequency of its serial clock outputis less 1/4 than the SPI Core clock input (PCLK) and its slave select output is edge-active trigger.