NUC502Apr 30, 2015 Page 230 of 266 Rev 1.16.15.3 Block DiagramTX_FIFO(64/16)UARTControllerBaud RateGeneratorRx shiftregisterTx shiftregisterAPB BUSExternal clock SINSOUTRX_FIFO(64/16)6.15.4 Functional Blocks DescriptionsTX_FIFOThe transmitter is buffered with a 64/16 byte FIFO to reduce the number ofinterrupts presented to the CPU.RX_FIFOThe receiver is buffered with a 64/16 byte FIFO (plus three error bits per byte)to reduce the number of interrupts presented to the CPU.TX shift RegisterShifting the transmitting data out seriallyRX shift RegisterShifting the receiving data in seriallyModem Control RegisterThis register controls the interface to the MODEM or data set (or a peripheraldevice emulating a MODEM).Modem Status RegisterThis register provides the current status of the control lines from the MODEMand cause the MODEM status interrupt (CTS# or DSR# or RI# or DCD#)Note: Only CTS#/RTS# can be used in this version.Baud Rate GeneratorDividing the external clock by the divisor to get the desired internal clock
