Xilinx Alveo U50 User Manual
Also see for Alveo U50: User guideInstallation guideInstallation guide
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Contents
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Creating an MCS File and Programming theAlveo CardFor custom RTL flow, this section outlines the procedures to do the following:• Create an MCS file (PROM image)• Flash program through the maintenance connectorCreate an MCS File (PROM Image)To ensure that the PROM image is successfully loaded onto the Alveo accelerator card at poweron, the starting address must be set to 0x01002000 and the interface set to spix4 whencreating the MCS file. Details on adding this to the MCS file can be found in the UltraScaleArchitecture Configuration User Guide (UG570).The Alveo accelerator card's Quad SPI configuration flash memory contains a protected region,with the factory base image at the 0x00000000 address space. This base image points to thecustomer programmable region at a 0x01002000 address space offset.In addition, the following code must be placed in the project XDC file to correctly configure theMCS file.# Bitstream Configuration# ------------------------------------------------------------------------set_property CONFIG_VOLTAGE 1.8 [current_design]set_property BITSTREAM.CONFIG.CONFIGFALLBACK Enable [current_design]set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]set_property CONFIG_MODE SPIx4 [current_design]set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design]set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN disable [current_design]set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR Yes [current_design]# ------------------------------------------------------------------------Once the XDC file has been updated, generate the MCS file using the following command (notethe quotations are required):write_cfgmem -force -format mcs -interface spix4 -size 1024 -loadbit "up 0x01002000 |
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