Xilinx Alveo U50 User Manual
Also see for Alveo U50: User guideInstallation guideInstallation guide
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Table 4: Card Status LEDsReference Designator DescriptionES ProductionDS1 When FPGA is configured, LED is blue, otherwise it remains OffDS2 System healthy when green1 Not populatedDS3 Warning or alarm when orange1 Not populatedDS4 Power fault when red Not populatedNotes:1. Functionality is not yet defined.Ethernet status LEDs are located on the top-left, front panel above the SFP-DD modules. TheLED definitions are given in the following tables.Table 5: ES Ethernet Status LEDsReference Designator DescriptionSFPDD_0_ACT Dedicated to Activity and is only green1SFPDD_0_STA Dedicated to Link and is yellow/green1SFPDD_1_ACT Dedicated to Activity and is only green1SFPDD_1_STA Dedicated to Link and is yellow/green1Notes:1. Functionality is not yet defined.Table 6: PQ Ethernet Status LEDsReference DescriptionQSFP_0_ACT Dedicated to Activity and is only green1QSFP_0_STA Dedicated to Link and is yellow/green1Notes:1. Functionality is not yet defined.Card Power SystemThe Alveo U50 card has separate power rails for FPGA fabric and HBM memory. Developersmust ensure their designs do not draw too much power for each rail. More information can befound in the Known Issues table of the Alveo U50 Data Center Accelerator Card Installation Guide(UG1370). To monitor, limited power system telemetry is available through the I2C IP. I2C IP isinstantiated during the FPGA design process which begins after the Alveo Data Centeraccelerator card is selected from the Vivado Design Suite Boards tab. Refer to Design Flows formore information.Chapter 4: Card Component DescriptionUG1371 (v1.2) December 18, 2019 www.xilinx.comAlveo U50 Accelerator Card User Guide 19Send Feedback |
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