Xilinx Alveo U50 User Manual
Also see for Alveo U50: User guideInstallation guideInstallation guide
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For configuration details, see the UltraScale Architecture Configuration User Guide (UG570). Thedetailed FPGA and Flash pin connections for the feature described in this section aredocumented in the Alveo U50 accelerator card XDC file, referenced in Appendix A: Xilinx DesignConstraints (XDC) File.Maintenance Connector InterfaceThe Alveo U50 accelerator card provides access to the FPGA through the JTAG interface using adebug and maintenance board (DMB) connected to the 30-pin maintenance connector. Theconnector pinout supports three UART debug interfaces: PMBus, FPGA JTAG, and satellitecontroller JTAG. The following figure shows the maintenance connector interface. For moreinformation, see Alveo Programming Cable User Guide (UG1377).Figure 5: Maintenance ConnectorMaintenanceConnector2x15SatelliteControllerMSP432JTAG1SC_UART_RXD/TXDFPGA_TXD/RXD_MSPXLTXLTControl from SCJTAG0UART0X22955-072919XCU50FPGATIP: The Alveo Programming Cable is not provided with the U50 (QSFP) production card. This cable can bepurchased at the following link: https://www.xilinx.com/products/boards-and-kits/alveo/accessories.html.PCI Express EndpointThe Alveo U50 accelerator card implements a 16-lane PCI Express edge connector that performsdata transfers at the rate of 2.5 giga-transfers per second (GT/s) for Gen1, 5.0 GT/s for Gen2, 8.0GT/s for Gen3 applications, and 16.0 GT/s for Gen4 applications.Chapter 4: Card Component DescriptionUG1371 (v1.2) December 18, 2019 www.xilinx.comAlveo U50 Accelerator Card User Guide 17Send Feedback |
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