Xilinx Alveo U50 User Manual
Also see for Alveo U50: User guideInstallation guideInstallation guide
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Contents
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Chapter 4Card Component DescriptionThis chapter provides a functional description of the components of the Alveo™ U50 DataCenter accelerator card.UltraScale+ FPGAThe Alveo U50 accelerator card is populated with the 16 nm UltraScale+™ XCU50 FPGA.This UltraScale+ HBM device incorporates two 4 GB high-bandwidth memory (HBM) stacksadjacent to the device die. Using SSI technology, the device communicates to the HBM stacksthrough memory controllers that connect through the silicon interposer at the bottom of thedevice. Each XCU50 FPGA contains two 4 GB HBM stacks, resulting in up to 8 GB of HBM perdevice. The device includes 32 HBM AXI interfaces used to communicate with the HBM. Theflexible addressing feature that is provided by a built-in switch allows for any of the 32 HBM AXIinterfaces to access any memory address on either one or both of the HBM stacks. This flexibleconnection between the device and the HBM stacks is helpful for floorplanning and timingclosure.Note: The xilinx_u50_xdma_201920_2 platform allows a maximum of 30 of the 32 available HBM pseudochannels to be used. Using more will generate errors during hardware build. Xilinx recommends usingpseudo-channels 0:29 because pseudo channels 30 and 31 need to route across fabric resources sharedwith the static region possibly resulting in lower performance.Quad SPI Flash MemoryThe Quad SPI device provides 1 Gb of nonvolatile storage.• Part number: MT25QU01GBBB8E12-0AAT (Micron)• Supply voltage: 1.8V• Datapath width: 4 bits• Data rate: variableChapter 4: Card Component DescriptionUG1371 (v1.2) December 18, 2019 www.xilinx.comAlveo U50 Accelerator Card User Guide 16Send Feedback |
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