Xilinx Alveo U50 User Manual
Also see for Alveo U50: User guideInstallation guideInstallation guide
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Design FlowsThe preferred optimal design flow for targeting the Alveo Data Center accelerator card uses theVitis™ unified software platform. However, traditional design flows, such as RTL or HLx are alsosupported using the Vivado® Design Suite tools. The following figure shows a summary of thedesign flows.Figure 4: Alveo Data Center Accelerator Card Design FlowsHigh complexitySlowestHighSimplicityTime to MarketHardware Expertise RequiredComplexity abstractedFastestLowRTL Flow HLx Flow (IP integrator)Traditional FlowsTarget PlatformVitisX22272-020419Requirements for the different design flows are listed in the following table.Table 2: Requirements to Get Started with Alveo Data Center Accelerator Card DesignFlowsRTL Flow HLx Flow VitisFlow documentation UG9491 UG8952 UG14163Vivado tools support Board support XDC Board support XDC N/AProgramming the FPGA Vivado Hardware Manager Vivado Hardware Manager UG13704Notes:1. UltraFast Design Methodology Guide for the Vivado Design Suite (UG949).2. Vivado Design Suite User Guide: System-Level Design Entry (UG895). See “Using the Vivado Design Suite Platform BoardFlow” in Chapter 2 and Appendix A.3. Vitis Accelerated Flow in the Vitis Unified Software Platform Documentation (UG1416).4. Alveo U50 Data Center Accelerator Card Installation Guide (UG1370).Chapter 1: IntroductionUG1371 (v1.2) December 18, 2019 www.xilinx.comAlveo U50 Accelerator Card User Guide 9Send Feedback |
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