Xilinx Spartan-6 FPGA Series Design And Pin Planning Manual

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Xilinx Spartan-6 FPGA Series Design And Pin Planning Manual Manual pdf 19 page image

Spartan-6 FPGA PCB Design and Pin Planning www.xilinx.com 19UG393 (v1.1) April 29, 2010PCB Decoupling Capacitors0402 Ceramic CapacitorThe 0.47 μF 0402 capacitor covers the high-middle frequency range. Placement andmounting are critical for these capacitors.The capacitor should be mounted as close to the FPGA as possible (achieves the leastparasitic inductance possible).For PCBs with a total thickness of < 1.575 mm (62 mils), the best placement location is onthe PCB backside, within the device footprint (in the empty cross with an absence of vias).V CC and GND vias corresponding to the supply of interest should be identified in the viaarray. Where space is available, 0402 mounting pads should be added and connected tothese vias.For PCBs with a total thickness > 1.575 mm (62 mils), the best placement location could beon the PCB top surface. The depth of the V CC plane of interest in the PCB stackup is the keyfactor: if the V CC plane is in the PCB stackup’s top half, capacitor placement on the top PCBsurface is optimal; if the V CC plane is in the PCB stackup’s bottom half, capacitorplacement on the bottom PCB surface is optimal.Any 0402 capacitors placed outside the device footprint (whether on the top or bottomsurface) should be within 0.5 inch of the device’s outer edge.The capacitor mounting (solder lands, traces, and vias) must be optimized for lowinductance. Vias should be butted against the pads with no trace length in-between. Thesevias should be at the sides of the pads if at all possible (see Figure 2-2C). Via placement atthe sides of the pads decreases the mounting’s parasitic inductance by increasing themutual inductive coupling of one via to the other. Dual vias can be placed on both sides ofthe pads (see Figure 2-2D) for even lower parasitic inductance, but with diminishingreturns.Many manufacturing rules prevent mounting any device within 0.1 inch of the FPGA onthe PCB top surface. Manufacturing rules can also prevent capacitor placement on the PCBbackside within the device footprint, whether because backside mounting is prohibited orgeometries necessary to fit mounting pads in the tight spaces between vias are too smallfor reliable soldering. These rules decrease the available options for capacitor placementbut do not preclude meeting the Xilinx placement recommendations. Discuss any specificconcerns with a PCB fabrication, assembly, and/or quality department.