Xilinx Spartan-6 FPGA Series Design And Pin Planning Manual

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Xilinx Spartan-6 FPGA Series Design And Pin Planning Manual Manual pdf 40 page image

40 www.xilinx.com Spartan-6 FPGA PCB Design and Pin PlanningUG393 (v1.1) April 29, 2010Chapter 3: SelectIO Signalingis higher than the voltage of the P signal, the state is considered Low. Typically the P and Nsignals have similar swing, and have a common-mode voltage above GND (although thisis not always the case). LVDS is one common example of a differential I/O standard.SDR versus DDR InterfacesThe difference between Single Data Rate (SDR) and Double Data Rate (DDR) interfaces hasto do with the relationship of the data signals of a bus to the clock signal of that bus. In SDRsystems, data is only registered at the input flip-flops of a receiving device on either therising or the falling edge of the clock. One full clock period is equivalent to one bit time. InDDR systems, data is registered at the input flip-flops of a receiving device on both therising and falling edges of the clock. One full clock period is equivalent to two bit times.The distinction of SDR and DDR has nothing to do with whether the I/O standard carryingthe signals is single-ended or differential. A single-ended interface can be SDR or DDR,and a differential interface can also be SDR or DDR.Single-Ended SignalingA variety of single-ended I/O standards are available in the Spartan-6 FPGA IOBconfiguration options.Modes and AttributesSome of these I/O standards can be used only in unidirectional mode, while some can beused in bidirectional mode or unidirectional mode.Some I/O standards have attributes to control drive strength and slew rate, as well as thepresence of weak pull-up or pull-down, and weak-keeper circuits (not intended for use asparallel termination), and stronger input-termination resistors. Drive strength, slew rate,and in some cases specifying untuned output driver impedance can be used to tune aninterface for adequate speed while not overdriving the signals. Weak pull-ups, weak pull-downs, and weak keepers can be used to ensure a known or steady level on a floating or 3-stated signal. See the Spartan-6 FPGA SelectIO Resources User Guide for more information.Input ThresholdsThe input circuitry of the single-ended standards fall into two categories: those with fixedinput thresholds and those with input thresholds set by the V REF voltage. The use of VREFhas three advantages:• It allows for tighter control of input threshold levels• It removes dependence on die GND for the threshold reference• It allows for input thresholds to be closer together, which reduces the need for a largevoltage swing of the signal at the input receiverTwo 1.8V I/O standards that illustrate this are LVCMOS18 and SSTL18 Class 1. When aSpartan-6 FPGA is receiving, the input thresholds, V IL and V IH, are much closer togetherfor the SSTL18 standard.This smaller required swing allows for higher frequency of operation in the overall link. Asmaller swing at the driver means reduced DC power is required with less transientcurrent. The one drawback to the use of VREF is that the semi-dedicated VREF pins of thebank cannot be used as I/Os – they must all be connected to an external reference voltagewith a decoupling capacitor for each V REF pin. For more information on V REF decouplingand decoupling of all other supplies, see Chapter 2, Power Distribution System.