Xilinx Spartan-6 FPGA Series Design And Pin Planning Manual

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Xilinx Spartan-6 FPGA Series Design And Pin Planning Manual Manual pdf 38 page image

38 www.xilinx.com Spartan-6 FPGA PCB Design and Pin PlanningUG393 (v1.1) April 29, 2010Chapter 2: Power Distribution Systemmillimeters from the capacitor solder lands on the board, the current loop area is greaterthan necessary (see Figure 2-1A).To reduce the current loop area, vias should be placed directly against capacitor solderlands (see Figure 2-1B). Never connect vias to the lands with a section of trace (seeFigure 2-1A).Other improvements of geometry are via-in-pad (via under the solder land), not shown,and via-beside-pad (vias straddle the lands instead of being placed at the ends of thelands), shown in Figure 2-1C. Double vias also improve connecting trace geometry andcapacitor land geometry (see Figure 2-1D).Exceptionally thick boards (> 2.3 mm or 90 mils) have vias with higher parasiticinductance.To reduce the parasitic inductance, move critical V CC /GND plane sandwiches close to thetop surface where the FPGA is located, and place the highest frequency capacitors on thetop surface where the FPGA is located.Possibility 3: I/O Signals in PCB are Stronger Than NecessaryIf noise in the VCCO PDS is still too high after refining the PDS, the I/O interface slew ratecan be reduced. This applies to both outputs from the FPGA and inputs to the FPGA. Insevere cases, excessive overshoot on inputs to the FPGA can reverse-bias the IOB clampdiodes, injecting current into the V CCO PDS.If large amounts of noise are present on V CCO , the drive strength of these interfaces shouldbe decreased, or different termination should be used (on input or output paths).Possibility 4: I/O Signal Return Current Traveling in Sub-Optimal PathsI/O signal return currents can also cause excessive noise in the PDS. For every signaltransmitted by a device into the PCB (and eventually into another device), there is an equaland opposite current flowing from the PCB into the device's power/ground system. If alow-impedance return current path is not available, a less optimal, higher impedance pathis used. When I/O signal return currents flow over a less optimal path, voltage changes areinduced in the PDS, and the signal can be corrupted by crosstalk. This can be improved byensuring every signal has a closely spaced and fully intact return path.Methods to correct a sub-optimal return current path:• Restrict signals to fewer routing layers with verified continuous return current paths.• Provide low-impedance paths for AC currents to travel between reference planes(decoupling capacitors at PCB locations where layer transitions occur).