Xilinx Spartan-6 FPGA Series Design And Pin Planning Manual

Also see for Spartan-6 FPGA Series: Getting started User guide User guide User guide User guide

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Xilinx Spartan-6 FPGA Series Design And Pin Planning Manual Manual pdf 64 page image

64 www.xilinx.com Spartan-6 FPGA PCB Design and Pin PlanningUG393 (v1.1) April 29, 2010Chapter 6: I/O Pin and Clock PlanningGTP Transceiver Clocking ConsiderationsGTP transceivers use BUFIO2 clock buffers to reach the DCM, PLL, and BUFG resourcesfor FPGA logic clocking. From one to all eight BUFIO2s on a side can be used by the GTPtransceivers. Monitoring how many specific BUFIO2s are used ensures that the desiredpinout does not require more BUFIO2s than are available. The SelectIO interfaces and theGCLK pin to DCM/PLL connectivity also compete for the same BUFIO2 clock buffers asthe GTP transceivers. This is described in the BUFIO2 I/O Clock Buffer Usage section.The connectivity between the GTP transceiver output clocks and BUFIO2 is described inChapter 1 of the Spartan-6 FPGA Clocking Resources User Guide.PCI ExpressThe best designs define the pin placement and GTP transceiver usage with the integratedblock for PCI Express® before any other GTP transceiver based IP is planned. To ensureproper timing, the integrated block for PCI Express uses the closest GTP transceivers.Both the Core Generator tool and the Spartan-6 FPGA Integrated Endpoint Block for PCIExpress User Guide are helpful when defining the pin placement and GTP transceiverusage. The integrated block for PCI Express only allows using the GTP transceivers on thetop half of the device. The supported GTP transceiver locations are described in a table inthe Supported Core Pinouts section (Chapter 7) of the Spartan-6 FPGA Integrated EndpointBlock for PCI Express User Guide.Other GTP Transceiver Based ToolsTo support the desired core, and ensure enough GTP transceivers are available, use theCore Generator tool to generate valid pin placements for Xilinx provided cores. Multi-lanecores require adjacent GTP transceivers.Global and I/O ClockingDefining the best clocking structure for a design is an important aspect of pin planning.Before locking the pin placement, the designer must make sure that the design does notrequire more clock buffers or clock I/O pins than are available in any given region, andthat the connectivity is valid. For simple designs, those with only a few I/O, global, or GTPtransceiver derived clocks, this determination can be accomplished using the guidelines inthis chapter. For designs with a high utilization of clock resources in any given region, theI/O interfaces, clock structures, and any IP required specific clock buffers should beentered into the design and run through the ISE software. The ISE software provides thedesign rule checks (DRCs) for valid clock usage and I/O pin assignments.GCLK Pin AssignmentThe memory controller blocks, the PCI core interfaces, and the 16-bit wide configurationmodes all share multi-function pins with GCLKs. The availability of GCLK pins for a givenpackage should be checked to ensure that the pins are not needed for other sharedfunctions.The clock column in the PlanAhead Package Pins view can group all the GCLK pins in asingle list by deselecting the Group by I/O Bank icon on the left, and then using the clockheader to sort the column.