Xilinx Virtex-6 FPGA User Manual
Also see for Virtex-6 FPGA: User guideUser guideGuideHardware setup guideUser guide
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Virtex-6 FPGA System Monitor www.xilinx.com 25UG370 (v1.1) June 14, 2010System Monitor Control LogicJTAGLOCKED signal is activated by writing 0001h to DRP address 00h. TheJTAGLOCKED signal is reset again by writing 0000h to DRP address 00h.System Monitor Control LogicMany of the most commonly used system monitoring functions are implemented in theSystem Monitor control logic. Common functions include:• Channel sequencer• Measurement averaging• Maximum and minimum internal sensor measurements• Automatic alarms on internal sensors• Sensor and ADC calibrationThe control logic also decodes the configuration registers to configure the ADC samplingmodes (see System Monitor Timing, page 33) and external analog-input configuration (seeAnalog Inputs, page 39).Channel SequencerWhen bits SEQ1 and SEQ0 in Control Register 41h are set to logic 1 (see Table 9, page 20),System Monitor operates in Single Channel mode. In this mode, the user must select thechannel for Analog-to-Digital conversion by writing to the bit locations CH0 to CH4 incontrol register 40h. Operating modes for Single Channel mode, such as analog inputmode (BU) and acquisition time (ACQ), must also be set by writing to Control Register40h. In applications where many channels need to be monitored, this can mean asignificant overhead for the microprocessor or other controller. To automate this task, afunction called the Channel Sequencer is provided.The Channel Sequencer provides a method for the user to set up a predefined sequence ofchannels (both internal and external) to be automatically monitored. The ChannelSequencer function is implemented using eight control registers from address 48h to 4Fhon the DRP (see Control Registers, page 17). These eight registers can be viewed as fourpairs of 16-bit registers. Each pair of registers controls one aspect of the sequencerfunctionality. Individual bits in each pair of registers (32 bits) enable a specific functionalityfor a particular ADC channel. The four pairs of registers are:• ADC channel selection (48h and 49h)• ADC channel averaging enables (4Ah and 4Bh)• ADC channel analog-input mode (4Ch and 4Dh)• ADC channel acquisition time (4Eh and 4Fh)System Monitor only operates in Continuous Sampling mode (see Continuous Sampling,page 34) when the automatic channel sequencer is enabled. Sequencer mode is enabled byusing bits SEQ1 and SEQ0 in Configuration register 1 (see Configuration Registers (40h to42h), page 17). The Channel Sequencer registers should be initialized by the user whenSystem Monitor is instantiated in a design (see System Monitor Primitive, page 8). TheChannel Sequencer can also be reconfigured via the DRP at run time. The Sequencer mustfirst be disabled by writing to bits SEQ1 and SEQ0 before writing to any of the ChannelSequencer registers. It is recommended the System Monitor is placed in safe mode bywriting zeros to SEQ0 and SEQ1 while updating the Control Registers. System Monitor isautomatically reset whenever SEQ1 and SEQ0 are changed. The current status registerwww.BDTIC.com/XILINX |
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