Xilinx Virtex-6 FPGA User Manual
Also see for Virtex-6 FPGA: User guideUser guideGuideHardware setup guideUser guide
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Virtex-6 FPGA System Monitor www.xilinx.com 49UG370 (v1.1) June 14, 2010Application Guidelinesanalog power supply and ground reference are also routed into the center of the BGAusing traces. No power planes are required to supply a ground reference for SystemMonitor. The analog supply and ground reference are connected to the external referenceIC as shown in Figure 24, page 46. In the PCB implementation shown in Figure 28, thesupply and ground traces are routed on either side of the reference traces on the samesignal layer and act as guards between the reference traces and any potential aggressors(e.g., clocks and switching I/Os). It is not a requirement that the supply and ground tracesare routed on the same signal layer as shown, but they should be routed on an adjacentlayer. The V REFN and AV SS traces should be connected at (or close to) the ground pin of thereference IC. The ferrite bead that connects the analog ground trace to system groundshould also be placed close to the reference IC. Also shown in Figure 28 is the routing (fromthe top) of the dedicated analog input pair (VP and VN ). These inputs are also routed as adifferential pair.The external reference IC should be placed as close as possible to the FPGA to reduce theopportunities for coupled noise and to minimize any impedances in the reference traces.The staggered via field also allows the 10 nF decoupling on V REFP and AV DD to be placedin the center of the array close to the package balls. V REFP should be decoupled to VREFNand AV DD to AVSS near the package balls.When using the on-chip reference, the layout of the PCB is greatly simplified. The VREFPand V REFN pins should be shorted to AGND locally at the package balls - see Figure 24,page 46. The ferrite beads used to separate AGND and digital GND should be placed closeto the System Monitor balls in the center of the array along with a 10 nF decouplingcapacitor for AV DD .Figure 27 and Figure 28 are only intended to guide a PC board implementation. If it isfeasible to create an analog reference plane, then there is no issue with doing this.However, the reference inputs should still be routed as differential pairs as shown.Example Instantiation of SYSMONThe following sample design is intended to illustrate a basic instantiation of the Virtex-6FPGA System Monitor in a design (refer to System Monitor Primitive, page 8 for details onthe System Monitor I/O and attributes). Figure 29 illustrates a block diagram of the sampledesign. In this design, SYSMON is set up to monitor the VCCAUX supply and generate analarm on ALM[2], if the monitored supply moves outside the specified limits. Themeasured value of V CCAUX can be checked at any time on the DO bus. The design requiresan external clock to be provided. This design uses a 50 MHz external clock.Note: Because an internal clock divider is provided, a clock in the range 2 MHz to 200 MHz can beused as a clock source.The BUSY signal is also brought out so the ADC conversion rate is easily monitored. TheBUSY signal is also used to clock the DO data into a logic analyzer or other data acquisitionsystem for inspection. By varying the VCCAUX supply on the board, the alarm can betriggered or the varying supply voltage can be monitored on the DO bus.www.BDTIC.com/XILINX |
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