Xilinx Virtex-6 FPGA User Manual
Also see for Virtex-6 FPGA: User guideUser guideGuideHardware setup guideUser guide
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Virtex-6 FPGA System Monitor www.xilinx.com 27UG370 (v1.1) June 14, 2010System Monitor Control LogicADC Channel Averaging (4Ah and 4Bh)The ADC channel averaging registers enable and disable the averaging of the channel datain the sequence. The result of a measurement on an averaged channel is generated by using16, 64, or 256 samples. The amount of averaging is selected by using the AVG1 and AVG0bits in Configuration register 0 (see Configuration Registers (40h to 42h), page 17). Not allchannels in the automatic sequence have an averaging feature. The bit definitions for theseregisters are described in Table 15 and Table 16. Each bit in the two 16-bit registers is usedto enable or disable the averaging for its associated channel. A logic 1 enables averagingfor a particular channel in the sequence. All channels have the same amount of averagingapplied as defined by AVG1 and AVG0 (see Table 8, page 20).Averaging can be independently selected for each channel in the sequence. Whenaveraging is enabled for some of the channels of the sequence, the EOS will only be pulsedafter the sequence has completed the amount of averaging selected by using AVG1 andAVG0. If a channel in the sequence does not have averaging enabled, its status register willbe updated for every pass through the sequencer. When a channel has averaging enabled,its status register is only updated after the averaging is complete. An example sequence isTemperature and VAUX [1] and averaging of 16 is enabled on VAUX[1]. The sequence will beTemperature, VAUX[1], Temperature, VAUX[1], ... Temperature, VAUX[1] for each of theconversions where the temperature status register is updated. The VAUX [1] status registeris updated after the averaging of the 16 conversions.If averaging is enabled for the calibration channel (by setting CAVG logic Low), thecoefficients will be updated after the first pass through the sequence. Subsequent updatesto coefficient registers will require 16 conversions before the coefficients are updated.12 4 20 VAUXP[4],VAUXN[4]—Auxiliary channel 513 5 21 VAUXP[5],VAUXN[5]—Auxiliary channel 614 6 22 VAUXP[6],VAUXN[6]—Auxiliary channel 715 7 23 VAUXP[7],VAUXN[7]—Auxiliary channel 816 8 24 VAUXP[8],VAUXN[8]—Auxiliary channel 917 9 25 VAUXP[9],VAUXN[9]—Auxiliary channel 1018 10 26 VAUXP[10],VAUXN[10]—Auxiliary channel 1119 11 27 VAUXP[11],VAUXN[11]—Auxiliary channel 1220 12 28 VAUXP[12],VAUXN[12]—Auxiliary channel 1321 13 29 VAUXP[13],VAUXN[13]—Auxiliary channel 1422 14 30 VAUXP[14],VAUXN[14]—Auxiliary channel 1523 15 31 VAUXP[15],VAUXN[15]—Auxiliary channel 16Table 14: Sequencer ADC Channel Selection, Control Register 49h (Cont’d)SequenceNumber Bit ADCChannel Descriptionwww.BDTIC.com/XILINX |
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