Xilinx Virtex-6 FPGA User Manual
Also see for Virtex-6 FPGA: User guideUser guideGuideHardware setup guideUser guide
                                                              | |
Contents
| 
Virtex-6 FPGA System Monitor www.xilinx.com 51UG370 (v1.1) June 14, 2010Application GuidelinesSYSMON AttributesIn the example, System Monitor is set up in an automatic channel sequence mode thatincludes the Calibration Channel and VCCAUX Channel. Averaging is enabled for theV CCAUX channel. Sixteen ADC conversion results on VCCAUX are used to generate theaveraged measurement. The lower and upper alarm thresholds for VCCAUX are 2.375V and2.625V respectively. The target conversion rate for the ADC is 200 kSPS (200 kHz).DO[15:0] Output DRP data output bus. The result of the ADC conversion on theVCCAUX channel is placed on this bus shortly after EOSpulses High (when DRDY does high). Refer to SystemMonitor Timing for more information.BUSY Output System Monitor busy. This logic signal goes High for theduration of the ADC conversion. The rising edge can be usedto latch the DO bus data into an external acquisition system,for example, a logic analyzer. BUSY also toggles at theconversion frequency of the ADC. In this example, theconversion rate is set to 192.3 kHz (refer to SYSMONAttributes).ALM[2] Output V CCAUX supply measurement alarm. The Alarm limits are setto 2.5 ± 5% in this example (2.375V and 2.625V). When thesupply moves outside these limits, ALM[2] goes active High.The output resets to Low again after the measured V CCAUXsupply is inside the limits.Table 20: SYSMON I/Os (Cont’d)Name I/O DescriptionTable 21: SYSMON AttributesAttribute Setting DescriptionINIT_40 1000h Set averaging to 16 (AVG1 = 0 & AVG0 = 1). Refer toFigure 9, page 18 and Table 6, page 18.INIT_41 20C7h Enable Auto Channel Sequence Mode (SEQ1 = 1 & SEQ0 =0). Enable Offset and Gain calibration on the Supply Sensor(CAL3 = 1 & CAL2 = 1). Enable VCCAUX Alarm (ALM[2]) bysetting ALM2 to 0. All other alarm bits are set to 1 to disable.See Figure 9 and Table 6 for more information.INIT_42 0A00h DCLK frequency is 50 MHz. Desired ADC conversion rateis 200 kSPS and requires 26 ADCCLK cycles to perform oneADC conversion. CD = 50 MHz/(26 x 200 kHz) = 9.6. Onlyintegers allowed set CD7 to CD0 (ADCCLK divider) to 10(0Ah). Actual ADC conversion rate is 192.3 kHz. Refer toFigure 9 and Table 6 for more information.INIT_48 0401h Select Calibration and VCCAUX Channel for the Sequencer(refer to ADC Channel Selection (48h and 49h), page 26.INIT_49 0000hINIT_4A 0400h Enable Averaging on the VCCAUX channel (refer to ADCChannel Averaging (4Ah and 4Bh), page 27.INIT_4B 0000hwww.BDTIC.com/XILINX |
This manual is suitable for:
manualsdatabase
Your AI-powered manual search engine