Xilinx Virtex-6 FPGA User Manual
Also see for Virtex-6 FPGA: User guideUser guideGuideHardware setup guideUser guide
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8 www.xilinx.com Virtex-6 FPGA System MonitorUG370 (v1.1) June 14, 2010System Monitor Primitivedata registers also store the maximum and minimum measurements for each of the on-chipsensors recorded since power up or the last user reset.In addition to monitoring the on-chip temperature for user-defined applications, SystemMonitor issues a special alarm called Over-Temperature (OT) if the FPGA temperatureexceeds a user specified temperature e.g., 100°C. By default the over temperature limit isset to 125°C. The over-temperature signal is deactivated when the device temperature fallsbelow a user-specified lower limit. If the FPGA power down feature is enabled, the FPGAenters power down when the OT signal becomes active. The FPGA powers up again whenthe alarm is deactivated (see Automatic Alarms, page 29).All System Monitor features are customizable at run time through the DynamicReconfiguration Port (DRP) and the System Monitor control registers. These controlregisters can also be initialized at design time when System Monitor is instantiated in adesign (see Register File Interface, page 14). For the latest information, including FAQs,software updates, and tutorials, refer to http://www.xilinx.com/systemmonitor.System Monitor PrimitiveSystem Monitor PortsFigure 2 illustrates the ports on the primitive (SYSMON) used to instantiate SystemMonitor in a design. A description of the ports is given in Table 1.X-Ref Target - Figure 2Figure 2: System Monitor PortsRESETCONVSTCLKCONVSTDI[15:0]DO[15:0]DADDR[6:0]DWEDENDCLKDRDYDynamicReconfiguration Port(DRP)CONTROLand CLOCKCHANNEL[4:0]JTAGBUSYJTAGMODIFIEDJTAGLOCKEDOTALM[2:0]EOCEOSBUSYSYSMONSTATUSALARMSExternalAnalogInputsVPVNVAUXP[15:0]VAUXN[15:0]UG370_02_060709www.BDTIC.com/XILINX |
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