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ADM5120

Brand: ADMtek | Category: Gateway
Table of contents
  1. revision history
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. ADMtek Inc
  8. chapter 1 product overview
  9. block diagram
  10. pin assignment
  11. Stream Cipher Scrambler/ De-scrambler
  12. Hashing Function
  13. Buffer Management
  14. VLAN
  15. Bandwidth control function
  16. Receive descriptors content
  17. USB 1.1 H OST C ONTROLLER
  18. DPLL
  19. Transfer Descriptor Format
  20. DMA operation
  21. function description
  22. chapter 4 register description
  23. S YSTEM AND I NTERRUPT R EGISTERS
  24. IRQ_raw_status, offset: 0x40
  25. FIQ_status, offset: 0x18
  26. S WITCH C ONTROL R EGISTER D ESCRIPTION
  27. SftReset, offset: 0x04
  28. PHY_St, offset: 0x14
  29. Mem_control, offset: 0x1c
  30. CPUp_conf, offset 0x24
  31. Port_conf1, offset 0x2c
  32. Reserved, offset: 0x34
  33. Reserved, offset: 0x3c
  34. ADDR_st0, offset 0x50
  35. BW_cntl0, offset 0x60
  36. PHY_cntl1, offset 0x6c
  37. PHY_cntl3, offset 0x80
  38. TOS_en, offset 0x8c
  39. PHY_cntl4, offset 0xA0
  40. Int_st, offset 0xB0
  41. Int_mask, offset 0xB4
  42. GPIO_conf0, offset 0xB8
  43. Swap_in, offset 0xC8
  44. receive_Lbaddr, offset 0xDc
  45. Timer, offset 0xF4
  46. port3_LED, offset 0x10c
  47. General Control , offset 0x00
  48. Interrupt Enable, offset 0x08
  49. Host General Control, offset 0x10
  50. SOF Frame number, offset 0x1C
  51. RH descriptor, offset 0x74
  52. Port x status, offset 0x78
  53. Host Descriptor Head Starting Address, offset 0x80
  54. MPMC Control register, offset 000h
  55. MPMC Config register, offset 008h
  56. MPMC Dynamic Refresh register, offset 024h
  57. MPMC Dynamic RAS register, offset 034h
  58. MPMC Dynamic RC register, offset 048h
  59. MPMC Static Extended Wait register, offset 080h
  60. MPMC Dynamic Ras Cas[0,1,2,3] register
  61. MPMC Static Wait Wen [0,1,2,3] register
  62. MPMC Static Wait Rd [0,1,2,3] register
  63. MPMC Static Wait Turn [0,1,2,3] register
  64. MPMC PeriphID5-7 register, offset FD4h, FD8h, FDCh
  65. MPMC PeriphID3 register, offset FECh
  66. MPMC PCellID1 register, offset FF4h
  67. UART receive status register/error clear register, offset 04h
  68. UART line control register, middle byte, offset 0ch
  69. UART flag register (UARTFR), offset 18h
  70. UARTIIR/UARTICR, offset 1ch
  71. A BSOLUTE M AXIMUM R ATINGS
  72. electrical specification
ADMtek categories
Gateway
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