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NEC PD78053 manuals

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PD78053

Brand: NEC | Category: Computer Hardware
Table of contents
  1. Table Of Contents
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. Table Of Contents
  8. Table Of Contents
  9. Table Of Contents
  10. Table Of Contents
  11. Table Of Contents
  12. Table Of Contents
  13. Table Of Contents
  14. Table Of Contents
  15. Table Of Contents
  16. Table Of Contents
  17. Table Of Contents
  18. Table Of Contents
  19. Table Of Contents
  20. CHAPTER 1 GENERAL ( PD78054 Subseries)
  21. Applications
  22. Quality Grade
  23. Pin Configuration (Top View)
  24. K/0 Series Expansion
  25. Block Diagram
  26. Outline of Function
  27. Differences between Standard Quality Grade Products and (A) Products
  28. CHAPTER 2 GENERAL ( PD78054Y Subseries)
  29. Ordering Information
  30. Mask Options
  31. CHAPTER 3 PIN FUNCTION ( PD78054 Subseries)
  32. PROM programming mode pins (PROM versions only)
  33. Description of Pin Functions
  34. P10 to P17 (Port 1)
  35. P30 to P37 (Port 3)
  36. P40 to P47 (Port 4)
  37. P70 to P72 (Port 7)
  38. P120 to P127 (Port 12)
  39. AV DD
  40. Input/output Circuits and Recommended Connection of Unused Pins
  41. Pin Input/Output Circuit of List
  42. CHAPTER 4 PIN FUNCTION ( PD78054Y Subseries)
  43. P00 to P07 (Port 0)
  44. P20 to P27 (Port 2)
  45. P50 to P57 (Port 5)
  46. P130 and P131 (Port 13)
  47. X1 and X2
  48. Pin Input/Output Circuit Types
  49. CHAPTER 5 CPU ARCHITECTURE
  50. Memory Map ( PD78053, 78053Y)
  51. Memory Map ( PD78054, 78054Y)
  52. Memory Map ( PD78P054)
  53. Memory Map ( PD78055, 78055Y)
  54. Memory Map ( PD78056, 78056Y)
  55. Memory Map ( PD78058, 78058Y)
  56. Memory Map ( PD78P058, PD78P058Y)
  57. Internal program memory space
  58. Internal data memory space
  59. Data memory addressing
  60. Data Memory Addressing ( PD78053, 78053Y)
  61. Data Memory Addressing ( PD78054, 78054Y)
  62. Data Memory Addressing ( PD78P054)
  63. Data Memory Addressing ( PD78055, 78055Y)
  64. Data Memory Addressing ( PD78056, 78056Y)
  65. Data Memory Addressing ( PD78058, 78058Y)
  66. Data Memory Addressing ( PD78P058, 78P058Y)
  67. Processor Registers
  68. Internal High-Speed RAM Area
  69. Stack Pointer Configuration
  70. General registers
  71. General Register Configuration
  72. Special Function Register (SFR)
  73. Special-Function Register List
  74. Instruction Address Addressing
  75. Immediate addressing
  76. Table indirect addressing
  77. Operand Address Addressing
  78. Register addressing
  79. Direct addressing
  80. Short direct addressing
  81. Special-Function Register (SFR) addressing
  82. Register indirect addressing
  83. Based addressing
  84. Based indexed addressing
  85. CHAPTER 6 PORT FUNCTIONS
  86. Port Functions ( PD78054 subseries)
  87. Port Functions ( PD78054Y subseries)
  88. Port Configuration
  89. P00 and P07 Block Diagram
  90. Port 1
  91. Port 2 ( PD78054 Subseries)
  92. P22 and P27 Block Diagram
  93. Port 2 ( PD78054Y Subseries)
  94. Port 3
  95. Port 4
  96. Port 5
  97. Port 6
  98. P60 to P63 Block Diagram
  99. Port 7
  100. P71 and P72 Block Diagram
  101. Port 12
  102. Port 13
  103. Port Function Control Registers
  104. Port Mode Register and Output Latch Settings when Using Dual-Functions
  105. Port Mode Register Format
  106. Pull-Up Resistor Option Register Format
  107. Memory Expansion Mode Register Format
  108. Key Return Mode Register Format
  109. Port Function Operations
  110. Operations on input/output port
  111. CHAPTER 7 CLOCK GENERATOR
  112. Block Diagram of Clock Generator
  113. Clock Generator Control Register
  114. Processor Clock Control Register Format
  115. Relationship between CPU Clock and Minimum Instruction Execution Time
  116. Oscillation Mode Selection Register Format
  117. System Clock Oscillator
  118. Subsystem clock oscillator
  119. Scaler
  120. Clock Generator Operations
  121. Main system clock operations
  122. Subsystem clock operations
  123. System clock and CPU clock switching procedure
  124. CHAPTER 8 16-BIT TIMER/EVENT COUNTER
  125. Timer/Event Counter Operations
  126. Bit Timer/Event Counter Functions
  127. Bit Timer/Event Counter Square-Wave Output Ranges
  128. Bit Timer/Event Counter Configuration
  129. Bit Timer/Event Counter Output Control Circuit Block Diagram
  130. INTP0/TI00 Pin Valid Edge and CR00 Capture Trigger Valid Edge
  131. Bit Timer/Event Counter Control Registers
  132. Timer Clock Selection Register 0 Format
  133. Bit Timer Mode Control Register Format
  134. Capture/Compare Control Register 0 Format
  135. Bit Timer Output Control Register Format
  136. Port Mode Register 3 Format
  137. External Interrupt Mode Register 0 Format
  138. Sampling Clock Select Register Format
  139. Bit Timer/Event Counter Operations
  140. Interval Timer Configuration Diagram
  141. PWM output operations
  142. Control Register Settings for PWM Output Operation
  143. Example of D/A Converter Configuration with PWM Output
  144. PPG output operations
  145. Pulse width measurement operations
  146. Configuration Diagram for Pulse Width Measurement by Free-Running Counter
  147. Control Register Settings for Two Pulse Width Measurements with Free-Running Counter
  148. Two Capture Registers (with Rising Edge Specified)
  149. Control Register Settings for Pulse Width Measurement by Means of Restart
  150. External event counter operation
  151. External Event Counter Configuration Diagram
  152. Square-wave output operation
  153. Square-Wave Output Operation Timing
  154. One-shot pulse output operation
  155. Timing of One-Shot Pulse Output Operation Using Software Trigger
  156. Control Register Settings for One-Shot Pulse Output Operation Using External Trigger
  157. Bit Timer/Event Counter Operating Precautions
  158. Capture Register Data Retention Timing
  159. Operation Timing of OVF0 Flag
  160. CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2
  161. Bit Timer/Event Counters 1 and 2 Interval Times
  162. Bit Timer/Event Counters 1 and 2 Square-Wave Output Ranges
  163. bit timer/event counter mode
  164. Bit Timer/Event Counters 1 and 2 Configurations
  165. Bit Timer/Event Counters 1 and 2 Block Diagram
  166. Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 1
  167. Bit Timer/Event Counters 1 and 2 Control Registers
  168. Timer Clock Select Register 1 Format
  169. Bit Timer Mode Control Register 1 Format
  170. Bit Timer/Event Counters 1 and 2 Operations
  171. Bit Timer/Event Counter 1 Interval Time
  172. Bit Timer/Event Counter 2 Interval Time
  173. External Event Counter Operation Timings (with Rising Edge Specified)
  174. Interval Timer Operation Timing
  175. Interval Times when 2-Channel 8-Bit Timer/ Event Counters (TM1 and TM2) are Used as 16-Bit Timer/Event Counter
  176. Square-Wave Output Ranges when 2-Channel 8-Bit Timer/ Event Counters (TM1 and TM2 are Used as 16-Bit Timer/Event Counter
  177. Cautions on 8-Bit Timer/Event Counters 1 and 2
  178. Event Counter Operation Timing
  179. CHAPTER 10 WATCH TIMER
  180. Watch Timer Configuration
  181. Watch Timer Block Diagram
  182. Timer Clock Select Register 2 Format
  183. Watch Timer Mode Control Register Format
  184. Watch Timer Operations
  185. CHAPTER 11 WATCHDOG TIMER
  186. Interval Times
  187. Watchdog Timer Configuration
  188. Watchdog Timer Control Registers
  189. Watchdog Timer Mode Register Format
  190. Watchdog Timer Operations
  191. Interval timer operation
  192. CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT
  193. Clock Output Control Circuit Configuration
  194. Clock Output Function Control Registers
  195. Timer Clock Select Register 0 Format
  196. CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT
  197. Buzzer Output Function Control Registers
  198. CHAPTER 14 A/D CONVERTER
  199. A/D Converter Block Diagram
  200. A/D Converter Control Registers
  201. A/D Converter Mode Register Format
  202. A/D Converter Input Select Register Format
  203. External Interrupt Mode Register 1 Format
  204. A/D Converter Operations
  205. A/D Converter Basic Operation
  206. Input voltage and conversion results
  207. A/D converter operating mode
  208. A/D Conversion by Software Start
  209. A/D Converter Cautions
  210. Analog Input Pin Disposition
  211. A/D Conversion End Interrupt Request Generation Timing
  212. CHAPTER 15 D/A CONVERTER
  213. D/A Converter Configuration
  214. D/A Converter Control Registers
  215. Operations of D/A Converter
  216. Cautions Related to D/A Converter
  217. CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78054 Subseries)
  218. Serial Interface Channel 0 Functions
  219. Serial Bus Interface (SBI) System Configuration Example
  220. Serial Interface Channel 0 Configuration
  221. Serial Interface Channel 0 Block Diagram
  222. Serial Interface Channel 0 Control Registers
  223. Timer Clock Select Register 3 Format
  224. Serial Operating Mode Register 0 Format
  225. Serial Bus Interface Control Register Format
  226. Interrupt Timing Specify Register Format
  227. Serial Interface Channel 0 Operations
  228. wire serial I/O mode operation
  229. Wire Serial I/O Mode Timings
  230. Circuit of Switching in Transfer Bit Order
  231. SBI mode operation
  232. SBI Transfer Timings
  233. Bus Release Signal
  234. Addresses
  235. Commands
  236. Acknowledge Signal
  237. BUSY and READY Signals
  238. RELT, CMDT, RELD, and CMDD Operations (Master)
  239. ACKT Operation
  240. ACKE Operations
  241. ACKD Operations
  242. Various Signals in SBI Mode
  243. Pin Configuration
  244. Address Transmission from Master Device to Slave Device (WUP = 1)
  245. Command Transmission from Master Device to Slave Device
  246. Data Transmission from Master Device to Slave Device
  247. Data Transmission from Slave Device to Master Device
  248. Serial Bus Configuration Example Using 2-Wire Serial I/O Mode
  249. RELT and CMDT Operations
  250. SCK0/P27 pin output manipulation
  251. CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries)
  252. Serial Interface Channel 0 Interrupt Request Signal Generation
  253. Operation stop mode
  254. Start Condition
  255. Stop Condition
  256. Wait Signal
  257. Data Transmission from Master to Slave (Both Master and Slave Selected 9-Clock Wait)
  258. Data Transmission from Slave to Master (Both Master and Slave Selected 9-Clock Wait)
  259. Start Condition Output
  260. Slave Wait Release (Transmission)
  261. Slave Wait Release (Reception)
  262. SCK0/SCL/P27 pin output manipulation
  263. Logic Circuit of SCL Signal
  264. CHAPTER 18 SERIAL INTERFACE CHANNEL 1
  265. Serial Interface Channel 1 Configuration
  266. Serial Interface Channel 1 Block Diagram
  267. Serial Interface Channel 1 Control Registers
  268. Serial Operation Mode Register 1 Format
  269. Automatic Data Transmit/Receive Control Register Format
  270. Automatic Data Transmit/Receive Interval Specify Register Format
  271. Serial Interface Channel 1 Operations
  272. wire serial I/O mode operation with automatic transmit/receive function
  273. Basic Transmission/Reception Mode Operation Timings
  274. Basic Transmission/Reception Mode Flowchart
  275. Basic Transmission Mode Operation Timings
  276. Basic Transmission Mode Flowchart
  277. Repeat Transmission Mode Operation Timing
  278. Repeat Transmission Mode Flowchart
  279. Automatic Transmission/Reception Suspension and Restart
  280. System Configuration When the Busy Control Option is Used
  281. Operation Timings when Using Busy Control Option (BUSY0 = 0)
  282. Busy Signal and Wait Cancel (when BUSY0 = 0)
  283. Operation Timings when Using Busy & Strobe Control Option (BUSY0 = 0)
  284. Automatic Data Transmit/Receive Interval
  285. Operation Timing with Automatic Data Transmit/Receive Function Performed by Internal Clock
  286. Interval Timing Through CPU Processing (when the external clock is operating)
  287. CHAPTER 19 SERIAL INTERFACE CHANNEL 2
  288. Serial Interface Channel 2 Configuration
  289. Serial Interface Channel 2 Block Diagram
  290. Baud Rate Generator Block Diagram
  291. Serial Interface Channel 2 Control Registers
  292. Asynchronous Serial Interface Mode Register Format
  293. Serial Interface Channel 2 Operating Mode Settings
  294. Asynchronous Serial Interface Status Register Format
  295. Baud Rate Generator Control Register Format
  296. Relation between Main System Clock and Baud Rate
  297. Serial Interface Channel 2 Operation
  298. Asynchronous serial interface (UART) mode
  299. Relation between ASCK Pin Input Frequency and Baud Rate (When BRGC is set to 00H)
  300. Asynchronous Serial Interface Transmit/Receive Data Format
  301. Asynchronous Serial Interface Transmission Completion Interrupt Request Generation Timing
  302. Receive Error Timing
  303. wire serial I/O mode
  304. Wire Serial I/O Mode Timing
  305. Limitations when UART mode is used
  306. Receive Buffer Register Read Disable Period
  307. CHAPTER 20 REAL-TIME OUTPUT PORT
  308. Real-Time Output Port Configuration
  309. Real-time Output Buffer Register Configuration
  310. Real-Time Output Port Control Registers
  311. Real-time Output Port Control Register Format
  312. CHAPTER 21 INTERRUPT AND TEST FUNCTIONS
  313. Interrupt Sources and Configuration
  314. Basic Configuration of Interrupt Function
  315. Interrupt Function Control Registers
  316. Interrupt Request Flag Register Format
  317. Interrupt Mask Flag Register Format
  318. Priority Specify Flag Register Format
  319. Noise Eliminator Input/Output Timing (during rising edge detection)
  320. Program Status Word Configuration
  321. Interrupt Servicing Operations
  322. Flowchart of Generation from Non-Maskable Interrupt Request to Acknowledgment
  323. Non-Maskable Interrupt Request Acknowledge Operation
  324. Maskable interrupt request acknowledge operation
  325. Interrupt Request Acknowledge Processing Algorithm
  326. Interrupt Request Acknowledge Timing (Minimum Time)
  327. Software interrupt request acknowledge operation
  328. Multiple Interrupt Example
  329. Interrupt request reserve
  330. Test Functions
  331. Format of Interrupt Request Flag Register 1L
  332. Test input signal acknowledge operation
  333. CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION
  334. Memory Map when Using External Device Expansion Function
  335. External Device Expansion Function Control Register
  336. Memory Size Switching Register Format
  337. External Device Expansion Function Timing
  338. Instruction Fetch from External Memory
  339. External Memory Read Timing
  340. External Memory Write Timing
  341. External Memory Read Modify Write Timing
  342. Example of Connection with Memory
  343. CHAPTER 23 STANDBY FUNCTION
  344. Standby function control register
  345. Standby Function Operations
  346. HALT Mode Clear upon Interrupt Request Generation
  347. HALT Mode Release by RESET Input
  348. STOP mode
  349. STOP Mode Release by Interrupt Request Generation
  350. Release by STOP Mode RESET Input
  351. CHAPTER 24 RESET FUNCTION
  352. Timing of Reset Input by RESET Input
  353. Hardware Status after Reset
  354. CHAPTER 25 ROM CORRECTION
  355. Correction Address Registers 0 and 1 Format
  356. ROM Correction Control Registers
  357. ROM Correction Application
  358. Initialization Routine
  359. ROM Correction Operation
  360. ROM Correction Example
  361. Program Execution Flow
  362. Program Transition Diagram (when two places are corrected)
  363. Cautions on ROM Correction
  364. CHAPTER 26 PD78P054, 78P058
  365. Differences between PD78P054 and 78P058
  366. Memory Size Switching Register ( PD78P054)
  367. Memory Size Switching Register ( PD78P058)
  368. Internal Expansion RAM Size Switching Register
  369. PROM Programming
  370. PROM write procedure
  371. Page Program Mode Timing
  372. Byte Program Mode Flowchart
  373. Byte Program Mode Timing
  374. PROM reading procedure
  375. Erasure Procedure ( PD78P054KK-T and 78P058KK-T Only)
  376. CHAPTER 27 INSTRUCTION SET
  377. Legends Used in Operation List
  378. Description of "operation" column
  379. Operation List
  380. Instructions Listed by Addressing Type
  381. APPENDIX A DIFFERENCES BETWEEN PD78054, 78054Y SUBSERIES AND PD78058F, 78058FY SUBSERIES
  382. A-1. Major differences between PD78054, 78054Y Subseries and PD78058F, 78058FY Subseries
  383. APPENDIX B DEVELOPMENT TOOLS
  384. B-1. Development Tool Configuration
  385. B.1 Language Processing Software
  386. B.2 PROM Writing Tools
  387. B.3 Debugging Tools
  388. B.3.2 Software
  389. B.5 Upgrading Former In-circuit Emulators for 78K/0 Series to IE-78001-R-A
  390. B-2. EV-9200GC-80 Drawing (For Reference Only)
  391. B-3. EV-9200GC-80 Footprint (For Reference Only)
  392. B-4. TGK-080SDW Drawing (For Reference) (unit: mm)
  393. APPENDIX C EMBEDDED SOFTWARE
  394. APPENDIX D REGISTER INDEX
  395. APPENDIX E REVISION HISTORY
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