NEC uPD78055 manuals
uPD78055
Table of contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- CHAPTER 1 GENERAL ( PD78054 Subseries)
- Applications
- Quality Grade
- Pin Configuration (Top View)
- K/0 Series Expansion
- Block Diagram
- Outline of Function
- Differences between Standard Quality Grade Products and (A) Products
- CHAPTER 2 GENERAL ( PD78054Y Subseries)
- Ordering Information
- Mask Options
- CHAPTER 3 PIN FUNCTION ( PD78054 Subseries)
- PROM programming mode pins (PROM versions only)
- Description of Pin Functions
- P10 to P17 (Port 1)
- P30 to P37 (Port 3)
- P40 to P47 (Port 4)
- P70 to P72 (Port 7)
- P120 to P127 (Port 12)
- AV DD
- Input/output Circuits and Recommended Connection of Unused Pins
- Pin Input/Output Circuit of List
- CHAPTER 4 PIN FUNCTION ( PD78054Y Subseries)
- P00 to P07 (Port 0)
- P20 to P27 (Port 2)
- P50 to P57 (Port 5)
- P130 and P131 (Port 13)
- X1 and X2
- Pin Input/Output Circuit Types
- CHAPTER 5 CPU ARCHITECTURE
- Memory Map ( PD78053, 78053Y)
- Memory Map ( PD78054, 78054Y)
- Memory Map ( PD78P054)
- Memory Map ( PD78055, 78055Y)
- Memory Map ( PD78056, 78056Y)
- Memory Map ( PD78058, 78058Y)
- Memory Map ( PD78P058, PD78P058Y)
- Internal program memory space
- Internal data memory space
- Data memory addressing
- Data Memory Addressing ( PD78053, 78053Y)
- Data Memory Addressing ( PD78054, 78054Y)
- Data Memory Addressing ( PD78P054)
- Data Memory Addressing ( PD78055, 78055Y)
- Data Memory Addressing ( PD78056, 78056Y)
- Data Memory Addressing ( PD78058, 78058Y)
- Data Memory Addressing ( PD78P058, 78P058Y)
- Processor Registers
- Internal High-Speed RAM Area
- Stack Pointer Configuration
- General registers
- General Register Configuration
- Special Function Register (SFR)
- Special-Function Register List
- Instruction Address Addressing
- Immediate addressing
- Table indirect addressing
- Operand Address Addressing
- Register addressing
- Direct addressing
- Short direct addressing
- Special-Function Register (SFR) addressing
- Register indirect addressing
- Based addressing
- Based indexed addressing
- CHAPTER 6 PORT FUNCTIONS
- Port Functions ( PD78054 subseries)
- Port Functions ( PD78054Y subseries)
- Port Configuration
- P00 and P07 Block Diagram
- Port 1
- Port 2 ( PD78054 Subseries)
- P22 and P27 Block Diagram
- Port 2 ( PD78054Y Subseries)
- Port 3
- Port 4
- Port 5
- Port 6
- P60 to P63 Block Diagram
- Port 7
- P71 and P72 Block Diagram
- Port 12
- Port 13
- Port Function Control Registers
- Port Mode Register and Output Latch Settings when Using Dual-Functions
- Port Mode Register Format
- Pull-Up Resistor Option Register Format
- Memory Expansion Mode Register Format
- Key Return Mode Register Format
- Port Function Operations
- Operations on input/output port
- CHAPTER 7 CLOCK GENERATOR
- Block Diagram of Clock Generator
- Clock Generator Control Register
- Processor Clock Control Register Format
- Relationship between CPU Clock and Minimum Instruction Execution Time
- Oscillation Mode Selection Register Format
- System Clock Oscillator
- Subsystem clock oscillator
- Scaler
- Clock Generator Operations
- Main system clock operations
- Subsystem clock operations
- System clock and CPU clock switching procedure
- CHAPTER 8 16-BIT TIMER/EVENT COUNTER
- Timer/Event Counter Operations
- Bit Timer/Event Counter Functions
- Bit Timer/Event Counter Square-Wave Output Ranges
- Bit Timer/Event Counter Configuration
- Bit Timer/Event Counter Output Control Circuit Block Diagram
- INTP0/TI00 Pin Valid Edge and CR00 Capture Trigger Valid Edge
- Bit Timer/Event Counter Control Registers
- Timer Clock Selection Register 0 Format
- Bit Timer Mode Control Register Format
- Capture/Compare Control Register 0 Format
- Bit Timer Output Control Register Format
- Port Mode Register 3 Format
- External Interrupt Mode Register 0 Format
- Sampling Clock Select Register Format
- Bit Timer/Event Counter Operations
- Interval Timer Configuration Diagram
- PWM output operations
- Control Register Settings for PWM Output Operation
- Example of D/A Converter Configuration with PWM Output
- PPG output operations
- Pulse width measurement operations
- Configuration Diagram for Pulse Width Measurement by Free-Running Counter
- Control Register Settings for Two Pulse Width Measurements with Free-Running Counter
- Two Capture Registers (with Rising Edge Specified)
- Control Register Settings for Pulse Width Measurement by Means of Restart
- External event counter operation
- External Event Counter Configuration Diagram
- Square-wave output operation
- Square-Wave Output Operation Timing
- One-shot pulse output operation
- Timing of One-Shot Pulse Output Operation Using Software Trigger
- Control Register Settings for One-Shot Pulse Output Operation Using External Trigger
- Bit Timer/Event Counter Operating Precautions
- Capture Register Data Retention Timing
- Operation Timing of OVF0 Flag
- CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2
- Bit Timer/Event Counters 1 and 2 Interval Times
- Bit Timer/Event Counters 1 and 2 Square-Wave Output Ranges
- bit timer/event counter mode
- Bit Timer/Event Counters 1 and 2 Configurations
- Bit Timer/Event Counters 1 and 2 Block Diagram
- Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 1
- Bit Timer/Event Counters 1 and 2 Control Registers
- Timer Clock Select Register 1 Format
- Bit Timer Mode Control Register 1 Format
- Bit Timer/Event Counters 1 and 2 Operations
- Bit Timer/Event Counter 1 Interval Time
- Bit Timer/Event Counter 2 Interval Time
- External Event Counter Operation Timings (with Rising Edge Specified)
- Interval Timer Operation Timing
- Interval Times when 2-Channel 8-Bit Timer/ Event Counters (TM1 and TM2) are Used as 16-Bit Timer/Event Counter
- Square-Wave Output Ranges when 2-Channel 8-Bit Timer/ Event Counters (TM1 and TM2 are Used as 16-Bit Timer/Event Counter
- Cautions on 8-Bit Timer/Event Counters 1 and 2
- Event Counter Operation Timing
- CHAPTER 10 WATCH TIMER
- Watch Timer Configuration
- Watch Timer Block Diagram
- Timer Clock Select Register 2 Format
- Watch Timer Mode Control Register Format
- Watch Timer Operations
- CHAPTER 11 WATCHDOG TIMER
- Interval Times
- Watchdog Timer Configuration
- Watchdog Timer Control Registers
- Watchdog Timer Mode Register Format
- Watchdog Timer Operations
- Interval timer operation
- CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT
- Clock Output Control Circuit Configuration
- Clock Output Function Control Registers
- Timer Clock Select Register 0 Format
- CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT
- Buzzer Output Function Control Registers
- CHAPTER 14 A/D CONVERTER
- A/D Converter Block Diagram
- A/D Converter Control Registers
- A/D Converter Mode Register Format
- A/D Converter Input Select Register Format
- External Interrupt Mode Register 1 Format
- A/D Converter Operations
- A/D Converter Basic Operation
- Input voltage and conversion results
- A/D converter operating mode
- A/D Conversion by Software Start
- A/D Converter Cautions
- Analog Input Pin Disposition
- A/D Conversion End Interrupt Request Generation Timing
- CHAPTER 15 D/A CONVERTER
- D/A Converter Configuration
- D/A Converter Control Registers
- Operations of D/A Converter
- Cautions Related to D/A Converter
- CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78054 Subseries)
- Serial Interface Channel 0 Functions
- Serial Bus Interface (SBI) System Configuration Example
- Serial Interface Channel 0 Configuration
- Serial Interface Channel 0 Block Diagram
- Serial Interface Channel 0 Control Registers
- Timer Clock Select Register 3 Format
- Serial Operating Mode Register 0 Format
- Serial Bus Interface Control Register Format
- Interrupt Timing Specify Register Format
- Serial Interface Channel 0 Operations
- wire serial I/O mode operation
- Wire Serial I/O Mode Timings
- Circuit of Switching in Transfer Bit Order
- SBI mode operation
- SBI Transfer Timings
- Bus Release Signal
- Addresses
- Commands
- Acknowledge Signal
- BUSY and READY Signals
- RELT, CMDT, RELD, and CMDD Operations (Master)
- ACKT Operation
- ACKE Operations
- ACKD Operations
- Various Signals in SBI Mode
- Pin Configuration
- Address Transmission from Master Device to Slave Device (WUP = 1)
- Command Transmission from Master Device to Slave Device
- Data Transmission from Master Device to Slave Device
- Data Transmission from Slave Device to Master Device
- Serial Bus Configuration Example Using 2-Wire Serial I/O Mode
- RELT and CMDT Operations
- SCK0/P27 pin output manipulation
- CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries)
- Serial Interface Channel 0 Interrupt Request Signal Generation
- Operation stop mode
- Start Condition
- Stop Condition
- Wait Signal
- Data Transmission from Master to Slave (Both Master and Slave Selected 9-Clock Wait)
- Data Transmission from Slave to Master (Both Master and Slave Selected 9-Clock Wait)
- Start Condition Output
- Slave Wait Release (Transmission)
- Slave Wait Release (Reception)
- SCK0/SCL/P27 pin output manipulation
- Logic Circuit of SCL Signal
- CHAPTER 18 SERIAL INTERFACE CHANNEL 1
- Serial Interface Channel 1 Configuration
- Serial Interface Channel 1 Block Diagram
- Serial Interface Channel 1 Control Registers
- Serial Operation Mode Register 1 Format
- Automatic Data Transmit/Receive Control Register Format
- Automatic Data Transmit/Receive Interval Specify Register Format
- Serial Interface Channel 1 Operations
- wire serial I/O mode operation with automatic transmit/receive function
- Basic Transmission/Reception Mode Operation Timings
- Basic Transmission/Reception Mode Flowchart
- Basic Transmission Mode Operation Timings
- Basic Transmission Mode Flowchart
- Repeat Transmission Mode Operation Timing
- Repeat Transmission Mode Flowchart
- Automatic Transmission/Reception Suspension and Restart
- System Configuration When the Busy Control Option is Used
- Operation Timings when Using Busy Control Option (BUSY0 = 0)
- Busy Signal and Wait Cancel (when BUSY0 = 0)
- Operation Timings when Using Busy & Strobe Control Option (BUSY0 = 0)
- Automatic Data Transmit/Receive Interval
- Operation Timing with Automatic Data Transmit/Receive Function Performed by Internal Clock
- Interval Timing Through CPU Processing (when the external clock is operating)
- CHAPTER 19 SERIAL INTERFACE CHANNEL 2
- Serial Interface Channel 2 Configuration
- Serial Interface Channel 2 Block Diagram
- Baud Rate Generator Block Diagram
- Serial Interface Channel 2 Control Registers
- Asynchronous Serial Interface Mode Register Format
- Serial Interface Channel 2 Operating Mode Settings
- Asynchronous Serial Interface Status Register Format
- Baud Rate Generator Control Register Format
- Relation between Main System Clock and Baud Rate
- Serial Interface Channel 2 Operation
- Asynchronous serial interface (UART) mode
- Relation between ASCK Pin Input Frequency and Baud Rate (When BRGC is set to 00H)
- Asynchronous Serial Interface Transmit/Receive Data Format
- Asynchronous Serial Interface Transmission Completion Interrupt Request Generation Timing
- Receive Error Timing
- wire serial I/O mode
- Wire Serial I/O Mode Timing
- Limitations when UART mode is used
- Receive Buffer Register Read Disable Period
- CHAPTER 20 REAL-TIME OUTPUT PORT
- Real-Time Output Port Configuration
- Real-time Output Buffer Register Configuration
- Real-Time Output Port Control Registers
- Real-time Output Port Control Register Format
- CHAPTER 21 INTERRUPT AND TEST FUNCTIONS
- Interrupt Sources and Configuration
- Basic Configuration of Interrupt Function
- Interrupt Function Control Registers
- Interrupt Request Flag Register Format
- Interrupt Mask Flag Register Format
- Priority Specify Flag Register Format
- Noise Eliminator Input/Output Timing (during rising edge detection)
- Program Status Word Configuration
- Interrupt Servicing Operations
- Flowchart of Generation from Non-Maskable Interrupt Request to Acknowledgment
- Non-Maskable Interrupt Request Acknowledge Operation
- Maskable interrupt request acknowledge operation
- Interrupt Request Acknowledge Processing Algorithm
- Interrupt Request Acknowledge Timing (Minimum Time)
- Software interrupt request acknowledge operation
- Multiple Interrupt Example
- Interrupt request reserve
- Test Functions
- Format of Interrupt Request Flag Register 1L
- Test input signal acknowledge operation
- CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION
- Memory Map when Using External Device Expansion Function
- External Device Expansion Function Control Register
- Memory Size Switching Register Format
- External Device Expansion Function Timing
- Instruction Fetch from External Memory
- External Memory Read Timing
- External Memory Write Timing
- External Memory Read Modify Write Timing
- Example of Connection with Memory
- CHAPTER 23 STANDBY FUNCTION
- Standby function control register
- Standby Function Operations
- HALT Mode Clear upon Interrupt Request Generation
- HALT Mode Release by RESET Input
- STOP mode
- STOP Mode Release by Interrupt Request Generation
- Release by STOP Mode RESET Input
- CHAPTER 24 RESET FUNCTION
- Timing of Reset Input by RESET Input
- Hardware Status after Reset
- CHAPTER 25 ROM CORRECTION
- Correction Address Registers 0 and 1 Format
- ROM Correction Control Registers
- ROM Correction Application
- Initialization Routine
- ROM Correction Operation
- ROM Correction Example
- Program Execution Flow
- Program Transition Diagram (when two places are corrected)
- Cautions on ROM Correction
- CHAPTER 26 PD78P054, 78P058
- Differences between PD78P054 and 78P058
- Memory Size Switching Register ( PD78P054)
- Memory Size Switching Register ( PD78P058)
- Internal Expansion RAM Size Switching Register
- PROM Programming
- PROM write procedure
- Page Program Mode Timing
- Byte Program Mode Flowchart
- Byte Program Mode Timing
- PROM reading procedure
- Erasure Procedure ( PD78P054KK-T and 78P058KK-T Only)
- CHAPTER 27 INSTRUCTION SET
- Legends Used in Operation List
- Description of "operation" column
- Operation List
- Instructions Listed by Addressing Type
- APPENDIX A DIFFERENCES BETWEEN PD78054, 78054Y SUBSERIES AND PD78058F, 78058FY SUBSERIES
- A-1. Major differences between PD78054, 78054Y Subseries and PD78058F, 78058FY Subseries
- APPENDIX B DEVELOPMENT TOOLS
- B-1. Development Tool Configuration
- B.1 Language Processing Software
- B.2 PROM Writing Tools
- B.3 Debugging Tools
- B.3.2 Software
- B.5 Upgrading Former In-circuit Emulators for 78K/0 Series to IE-78001-R-A
- B-2. EV-9200GC-80 Drawing (For Reference Only)
- B-3. EV-9200GC-80 Footprint (For Reference Only)
- B-4. TGK-080SDW Drawing (For Reference) (unit: mm)
- APPENDIX C EMBEDDED SOFTWARE
- APPENDIX D REGISTER INDEX
- APPENDIX E REVISION HISTORY
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